Annotation of sys/arch/i386/pci/opti82c558.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: opti82c558.c,v 1.7 2006/09/19 11:06:34 jsg Exp $ */
2: /* $NetBSD: opti82c558.c,v 1.2 2000/07/18 11:24:09 soda Exp $ */
3:
4: /*-
5: * Copyright (c) 1999 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10: * NASA Ames Research Center.
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: * 3. All advertising materials mentioning features or use of this software
21: * must display the following acknowledgement:
22: * This product includes software developed by the NetBSD
23: * Foundation, Inc. and its contributors.
24: * 4. Neither the name of The NetBSD Foundation nor the names of its
25: * contributors may be used to endorse or promote products derived
26: * from this software without specific prior written permission.
27: *
28: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38: * POSSIBILITY OF SUCH DAMAGE.
39: */
40:
41: /*
42: * Copyright (c) 1999, by UCHIYAMA Yasushi
43: * All rights reserved.
44: *
45: * Redistribution and use in source and binary forms, with or without
46: * modification, are permitted provided that the following conditions
47: * are met:
48: * 1. Redistributions of source code must retain the above copyright
49: * notice, this list of conditions and the following disclaimer.
50: * 2. The name of the developer may NOT be used to endorse or promote products
51: * derived from this software without specific prior written permission.
52: *
53: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
54: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
55: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
56: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
57: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
58: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
59: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
63: * SUCH DAMAGE.
64: */
65:
66: /*
67: * Support for the Opti 82c558 PCI-ISA bridge interrupt controller.
68: */
69:
70: #include <sys/param.h>
71: #include <sys/systm.h>
72: #include <sys/device.h>
73: #include <sys/malloc.h>
74:
75: #include <machine/intr.h>
76: #include <machine/bus.h>
77:
78: #include <dev/pci/pcivar.h>
79: #include <dev/pci/pcireg.h>
80: #include <dev/pci/pcidevs.h>
81:
82: #include <i386/pci/pcibiosvar.h>
83: #include <i386/pci/opti82c558reg.h>
84:
85: int opti82c558_getclink(pciintr_icu_handle_t, int, int *);
86: int opti82c558_get_intr(pciintr_icu_handle_t, int, int *);
87: int opti82c558_set_intr(pciintr_icu_handle_t, int, int);
88: int opti82c558_get_trigger(pciintr_icu_handle_t, int, int *);
89: int opti82c558_set_trigger(pciintr_icu_handle_t, int, int);
90:
91: const struct pciintr_icu opti82c558_pci_icu = {
92: opti82c558_getclink,
93: opti82c558_get_intr,
94: opti82c558_set_intr,
95: opti82c558_get_trigger,
96: opti82c558_set_trigger,
97: };
98:
99: struct opti82c558_handle {
100: pci_chipset_tag_t ph_pc;
101: pcitag_t ph_tag;
102: };
103:
104: static const int viper_pirq_decode[] = {
105: -1, 5, 9, 10, 11, 12, 14, 15
106: };
107:
108: static const int viper_pirq_encode[] = {
109: -1, /* 0 */
110: -1, /* 1 */
111: -1, /* 2 */
112: -1, /* 3 */
113: -1, /* 4 */
114: VIPER_PIRQ_5, /* 5 */
115: -1, /* 6 */
116: -1, /* 7 */
117: -1, /* 8 */
118: VIPER_PIRQ_9, /* 9 */
119: VIPER_PIRQ_10, /* 10 */
120: VIPER_PIRQ_11, /* 11 */
121: VIPER_PIRQ_12, /* 12 */
122: -1, /* 13 */
123: VIPER_PIRQ_14, /* 14 */
124: VIPER_PIRQ_15, /* 15 */
125: };
126:
127: int
128: opti82c558_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag,
129: pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp)
130: {
131: struct opti82c558_handle *ph;
132:
133: ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT);
134: if (ph == NULL)
135: return (1);
136:
137: ph->ph_pc = pc;
138: ph->ph_tag = tag;
139:
140: *ptagp = &opti82c558_pci_icu;
141: *phandp = ph;
142: return (0);
143: }
144:
145: int
146: opti82c558_getclink(pciintr_icu_handle_t v, int link, int *clinkp)
147: {
148:
149: if (VIPER_LEGAL_LINK(link - 1)) {
150: *clinkp = link - 1;
151: return (0);
152: }
153:
154: return (1);
155: }
156:
157: int
158: opti82c558_get_intr(pciintr_icu_handle_t v, int clink, int *irqp)
159: {
160: struct opti82c558_handle *ph = v;
161: pcireg_t reg;
162: int val;
163:
164: if (VIPER_LEGAL_LINK(clink) == 0)
165: return (1);
166:
167: reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);
168: val = VIPER_PIRQ(reg, clink);
169: *irqp = (val == VIPER_PIRQ_NONE) ? 0xff : viper_pirq_decode[val];
170:
171: return (0);
172: }
173:
174: int
175: opti82c558_set_intr(pciintr_icu_handle_t v, int clink, int irq)
176: {
177: struct opti82c558_handle *ph = v;
178: int shift;
179: pcireg_t reg;
180:
181: if (VIPER_LEGAL_LINK(clink) == 0 || VIPER_LEGAL_IRQ(irq) == 0)
182: return (1);
183:
184: reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);
185: shift = VIPER_PIRQ_SELECT_SHIFT * clink;
186: reg &= ~(VIPER_PIRQ_SELECT_MASK << shift);
187: reg |= (viper_pirq_encode[irq] << shift);
188: pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg);
189:
190: return (0);
191: }
192:
193: int
194: opti82c558_get_trigger(pciintr_icu_handle_t v, int irq, int *triggerp)
195: {
196: struct opti82c558_handle *ph = v;
197: pcireg_t reg;
198:
199: if (VIPER_LEGAL_IRQ(irq) == 0) {
200: /* ISA IRQ? */
201: *triggerp = IST_EDGE;
202: return (0);
203: }
204:
205: reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);
206: if ((reg >> (VIPER_CFG_TRIGGER_SHIFT + viper_pirq_encode[irq])) & 1)
207: *triggerp = IST_LEVEL;
208: else
209: *triggerp = IST_EDGE;
210:
211: return (0);
212: }
213:
214: int
215: opti82c558_set_trigger(pciintr_icu_handle_t v, int irq, int trigger)
216: {
217: struct opti82c558_handle *ph = v;
218: int shift;
219: pcireg_t reg;
220:
221: if (VIPER_LEGAL_IRQ(irq) == 0) {
222: /* ISA IRQ? */
223: return ((trigger != IST_LEVEL) ? 0 : 1);
224: }
225:
226: reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);
227: shift = (VIPER_CFG_TRIGGER_SHIFT + viper_pirq_encode[irq]);
228: if (trigger == IST_LEVEL)
229: reg |= (1 << shift);
230: else
231: reg &= ~(1 << shift);
232: pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg);
233:
234: return (0);
235: }
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