Annotation of sys/arch/i386/include/specialreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: specialreg.h,v 1.31 2007/05/29 21:01:56 tedu Exp $ */
! 2: /* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */
! 3:
! 4: /*-
! 5: * Copyright (c) 1991 The Regents of the University of California.
! 6: * All rights reserved.
! 7: *
! 8: * Redistribution and use in source and binary forms, with or without
! 9: * modification, are permitted provided that the following conditions
! 10: * are met:
! 11: * 1. Redistributions of source code must retain the above copyright
! 12: * notice, this list of conditions and the following disclaimer.
! 13: * 2. Redistributions in binary form must reproduce the above copyright
! 14: * notice, this list of conditions and the following disclaimer in the
! 15: * documentation and/or other materials provided with the distribution.
! 16: * 3. Neither the name of the University nor the names of its contributors
! 17: * may be used to endorse or promote products derived from this software
! 18: * without specific prior written permission.
! 19: *
! 20: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 21: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 22: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 23: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 24: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 25: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 26: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 27: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 28: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 29: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 30: * SUCH DAMAGE.
! 31: *
! 32: * @(#)specialreg.h 7.1 (Berkeley) 5/9/91
! 33: */
! 34:
! 35: /*
! 36: * Bits in 386 special registers:
! 37: */
! 38: #define CR0_PE 0x00000001 /* Protected mode Enable */
! 39: #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
! 40: #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
! 41: #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
! 42: #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
! 43: #define CR0_PG 0x80000000 /* PaGing enable */
! 44:
! 45: /*
! 46: * Bits in 486 special registers:
! 47: */
! 48: #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
! 49: #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */
! 50: #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
! 51: #define CR0_NW 0x20000000 /* Not Write-through */
! 52: #define CR0_CD 0x40000000 /* Cache Disable */
! 53:
! 54: /*
! 55: * Cyrix 486 DLC special registers, accessable as IO ports.
! 56: */
! 57: #define CCR0 0xc0 /* configuration control register 0 */
! 58: #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */
! 59: #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
! 60: #define CCR0_A20M 0x04 /* enables A20M# input pin */
! 61: #define CCR0_KEN 0x08 /* enables KEN# input pin */
! 62: #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */
! 63: #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */
! 64: #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */
! 65: #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */
! 66:
! 67: #define CCR1 0xc1 /* configuration control register 1 */
! 68: #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */
! 69: /* the remaining 7 bits of this register are reserved */
! 70:
! 71: /*
! 72: * bits in the pentiums %cr4 register:
! 73: */
! 74:
! 75: #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */
! 76: #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */
! 77: #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */
! 78: #define CR4_DE 0x00000008 /* debugging extension */
! 79: #define CR4_PSE 0x00000010 /* large (4MB) page size enable */
! 80: #define CR4_PAE 0x00000020 /* physical address extension enable */
! 81: #define CR4_MCE 0x00000040 /* machine check enable */
! 82: #define CR4_PGE 0x00000080 /* page global enable */
! 83: #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */
! 84: #define CR4_OSFXSR 0x00000200 /* enable SSE instructions (P6 & later) */
! 85: #define CR4_OSXMMEXCPT 0x00000400 /* enable SSE instructions (P6 & later) */
! 86:
! 87: /*
! 88: * CPUID "features" (and "extended features") bits:
! 89: */
! 90:
! 91: #define CPUID_FPU 0x00000001 /* processor has an FPU? */
! 92: #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
! 93: #define CPUID_DE 0x00000004 /* has debugging extension */
! 94: #define CPUID_PSE 0x00000008 /* has 4MB page size extension */
! 95: #define CPUID_TSC 0x00000010 /* has time stamp counter */
! 96: #define CPUID_MSR 0x00000020 /* has mode specific registers */
! 97: #define CPUID_PAE 0x00000040 /* has phys address extension */
! 98: #define CPUID_MCE 0x00000080 /* has machine check exception */
! 99: #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
! 100: #define CPUID_APIC 0x00000200 /* has enabled APIC */
! 101: #define CPUID_SYS1 0x00000400 /* has SYSCALL/SYSRET inst. (Cyrix) */
! 102: #define CPUID_SEP 0x00000800 /* has SYSCALL/SYSRET inst. (AMD/Intel) */
! 103: #define CPUID_MTRR 0x00001000 /* has memory type range register */
! 104: #define CPUID_PGE 0x00002000 /* has page global extension */
! 105: #define CPUID_MCA 0x00004000 /* has machine check architecture */
! 106: #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
! 107: #define CPUID_PAT 0x00010000 /* has page attribute table */
! 108: #define CPUID_PSE36 0x00020000 /* has 36bit page size extension */
! 109: #define CPUID_SER 0x00040000 /* has processor serial number */
! 110: #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
! 111: #define CPUID_B20 0x00100000 /* reserved */
! 112: #define CPUID_DS 0x00200000 /* Debug Store */
! 113: #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
! 114: #define CPUID_MMX 0x00800000 /* has MMX instructions */
! 115: #define CPUID_FXSR 0x01000000 /* has FXRSTOR instruction (Intel) */
! 116: #define CPUID_EMMX 0x01000000 /* has extended MMX (Cyrix; obsolete) */
! 117: #define CPUID_SSE 0x02000000 /* has SSE instructions */
! 118: #define CPUID_SSE2 0x04000000 /* has SSE2 instructions */
! 119: #define CPUID_SS 0x08000000 /* self-snoop */
! 120: #define CPUID_HTT 0x10000000 /* hyper-threading tech */
! 121: #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
! 122: #define CPUID_B30 0x40000000 /* reserved */
! 123: #define CPUID_SBF 0x80000000 /* signal break on FERR */
! 124:
! 125: /*
! 126: * Note: The 3DNOW flag does not really belong in this feature set since it is
! 127: * returned by the cpuid instruction when called with 0x80000001 in eax rather
! 128: * than 0x00000001, but cyrix3_cpu_setup() moves it to a reserved bit of the
! 129: * feature set for simplicity
! 130: */
! 131: #define CPUID_3DNOW 0x40000000 /* has 3DNow! instructions (AMD) */
! 132: #define CPUID_LONG 0x20000000 /* long mode (AMD64, ext cpuid) */
! 133:
! 134: #define CPUIDECX_SSE3 0x00000001 /* has SSE3 instructions */
! 135: #define CPUIDECX_MWAIT 0x00000008 /* Monitor/Mwait */
! 136: #define CPUIDECX_DSCPL 0x00000010 /* CPL Qualified Debug Store */
! 137: #define CPUIDECX_VMX 0x00000020 /* Virtual Machine Extensions */
! 138: #define CPUIDECX_EST 0x00000080 /* enhanced SpeedStep */
! 139: #define CPUIDECX_TM2 0x00000100 /* thermal monitor 2 */
! 140: #define CPUIDECX_CNXTID 0x00000400 /* Context ID */
! 141: #define CPUIDECX_CX16 0x00002000 /* has CMPXCHG16B instruction */
! 142: #define CPUIDECX_XTPR 0x00004000 /* xTPR Update Control */
! 143:
! 144: /*
! 145: * Model-specific registers for the i386 family
! 146: */
! 147: #define MSR_P5_MC_ADDR 0x000
! 148: #define MSR_P5_MC_TYPE 0x001
! 149: #define MSR_TSC 0x010
! 150: #define P5MSR_CTRSEL 0x011 /* P5 only (trap on P6) */
! 151: #define P5MSR_CTR0 0x012 /* P5 only (trap on P6) */
! 152: #define P5MSR_CTR1 0x013 /* P5 only (trap on P6) */
! 153: #define MSR_APICBASE 0x01b
! 154: #define MSR_EBL_CR_POWERON 0x02a
! 155: #define MSR_EBC_FREQUENCY_ID 0x02c /* Pentium 4 only */
! 156: #define MSR_TEST_CTL 0x033
! 157: #define MSR_BIOS_UPDT_TRIG 0x079
! 158: #define MSR_BBL_CR_D0 0x088 /* PII+ only */
! 159: #define MSR_BBL_CR_D1 0x089 /* PII+ only */
! 160: #define MSR_BBL_CR_D2 0x08a /* PII+ only */
! 161: #define MSR_BIOS_SIGN 0x08b
! 162: #define P6MSR_CTR0 0x0c1
! 163: #define P6MSR_CTR1 0x0c2
! 164: #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */
! 165: #define MSR_TEMPERATURE_TARGET 0x0ee
! 166: #define MSR_TEMPERATURE_TARGET_LOW_BIT 0x40000000
! 167: #define MSR_MTRRcap 0x0fe
! 168: #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
! 169: #define MSR_BBL_CR_DECC 0x118 /* PII+ only */
! 170: #define MSR_BBL_CR_CTL 0x119 /* PII+ only */
! 171: #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */
! 172: #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */
! 173: #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */
! 174: #define MSR_SYSENTER_CS 0x174
! 175: #define MSR_SYSENTER_ESP 0x175
! 176: #define MSR_SYSENTER_EIP 0x176
! 177: #define MSR_MCG_CAP 0x179
! 178: #define MSR_MCG_STATUS 0x17a
! 179: #define MSR_MCG_CTL 0x17b
! 180: #define P6MSR_CTRSEL0 0x186
! 181: #define P6MSR_CTRSEL1 0x187
! 182: #define MSR_PERF_STATUS 0x198 /* Pentium M */
! 183: #define MSR_PERF_CTL 0x199 /* Pentium M */
! 184: #define MSR_THERM_CONTROL 0x19a
! 185: #define MSR_THERM_INTERRUPT 0x19b
! 186: #define MSR_THERM_STATUS 0x19c
! 187: #define MSR_THERM_STATUS_VALID_BIT 0x80000000
! 188: #define MSR_THERM_STATUS_TEMP(msr) ((msr >> 16) & 0x7f)
! 189: #define MSR_THERM2_CTL 0x19d /* Pentium M */
! 190: #define MSR_MISC_ENABLE 0x1a0
! 191: #define MSR_DEBUGCTLMSR 0x1d9
! 192: #define MSR_LASTBRANCHFROMIP 0x1db
! 193: #define MSR_LASTBRANCHTOIP 0x1dc
! 194: #define MSR_LASTINTFROMIP 0x1dd
! 195: #define MSR_LASTINTTOIP 0x1de
! 196: #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
! 197: #define MSR_MTRRVarBase 0x200
! 198: #define MSR_MTRRphysMask0 0x201
! 199: #define MSR_MTRRphysBase1 0x202
! 200: #define MSR_MTRRphysMask1 0x203
! 201: #define MSR_MTRRphysBase2 0x204
! 202: #define MSR_MTRRphysMask2 0x205
! 203: #define MSR_MTRRphysBase3 0x206
! 204: #define MSR_MTRRphysMask3 0x207
! 205: #define MSR_MTRRphysBase4 0x208
! 206: #define MSR_MTRRphysMask4 0x209
! 207: #define MSR_MTRRphysBase5 0x20a
! 208: #define MSR_MTRRphysMask5 0x20b
! 209: #define MSR_MTRRphysBase6 0x20c
! 210: #define MSR_MTRRphysMask6 0x20d
! 211: #define MSR_MTRRphysBase7 0x20e
! 212: #define MSR_MTRRphysMask7 0x20f
! 213: #define MSR_MTRR64kBase 0x250
! 214: #define MSR_MTRR16kBase 0x258
! 215: #define MSR_MTRRfix16K_A0000 0x259
! 216: #define MSR_MTRR4kBase 0x268
! 217: #define MSR_MTRRfix4K_C8000 0x269
! 218: #define MSR_MTRRfix4K_D0000 0x26a
! 219: #define MSR_MTRRfix4K_D8000 0x26b
! 220: #define MSR_MTRRfix4K_E0000 0x26c
! 221: #define MSR_MTRRfix4K_E8000 0x26d
! 222: #define MSR_MTRRfix4K_F0000 0x26e
! 223: #define MSR_MTRRfix4K_F8000 0x26f
! 224: #define MSR_MTRRdefType 0x2ff
! 225: #define MSR_MC0_CTL 0x400
! 226: #define MSR_MC0_STATUS 0x401
! 227: #define MSR_MC0_ADDR 0x402
! 228: #define MSR_MC0_MISC 0x403
! 229: #define MSR_MC1_CTL 0x404
! 230: #define MSR_MC1_STATUS 0x405
! 231: #define MSR_MC1_ADDR 0x406
! 232: #define MSR_MC1_MISC 0x407
! 233: #define MSR_MC2_CTL 0x408
! 234: #define MSR_MC2_STATUS 0x409
! 235: #define MSR_MC2_ADDR 0x40a
! 236: #define MSR_MC2_MISC 0x40b
! 237: #define MSR_MC4_CTL 0x40c
! 238: #define MSR_MC4_STATUS 0x40d
! 239: #define MSR_MC4_ADDR 0x40e
! 240: #define MSR_MC4_MISC 0x40f
! 241: #define MSR_MC3_CTL 0x410
! 242: #define MSR_MC3_STATUS 0x411
! 243: #define MSR_MC3_ADDR 0x412
! 244: #define MSR_MC3_MISC 0x413
! 245:
! 246: /* AMD MSRs */
! 247: #define MSR_K6_EPMR 0xc0000086
! 248:
! 249: /*
! 250: * AMD K8 (Opteron) MSRs.
! 251: */
! 252: #define MSR_SYSCFG 0xc0000010
! 253:
! 254: #define MSR_EFER 0xc0000080 /* Extended feature enable */
! 255: #define EFER_SCE 0x00000001 /* SYSCALL extension */
! 256: #define EFER_LME 0x00000100 /* Long Mode Active */
! 257: #define EFER_LMA 0x00000400 /* Long Mode Enabled */
! 258: #define EFER_NXE 0x00000800 /* No-Execute Enabled */
! 259:
! 260: #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */
! 261: #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */
! 262: #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */
! 263: #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */
! 264:
! 265: #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */
! 266: #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */
! 267: #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */
! 268:
! 269: /*
! 270: * These require a 'passcode' for access. See cpufunc.h.
! 271: */
! 272: #define MSR_HWCR 0xc0010015
! 273: #define HWCR_FFDIS 0x00000040
! 274:
! 275: #define MSR_NB_CFG 0xc001001f
! 276: #define NB_CFG_DISIOREQLOCK 0x0000000000000004ULL
! 277: #define NB_CFG_DISDATMSK 0x0000001000000000ULL
! 278:
! 279: #define MSR_LS_CFG 0xc0011020
! 280: #define LS_CFG_DIS_LS2_SQUISH 0x02000000
! 281:
! 282: #define MSR_IC_CFG 0xc0011021
! 283: #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800
! 284:
! 285: #define MSR_DC_CFG 0xc0011022
! 286: #define DC_CFG_DIS_CNV_WC_SSO 0x00000004
! 287: #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400
! 288:
! 289: #define MSR_BU_CFG 0xc0011023
! 290: #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL
! 291: #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
! 292: #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL
! 293:
! 294: /*
! 295: * Constants related to MTRRs
! 296: */
! 297: #define MTRR_N64K 8 /* numbers of fixed-size entries */
! 298: #define MTRR_N16K 16
! 299: #define MTRR_N4K 64
! 300:
! 301: /*
! 302: * the following four 3-byte registers control the non-cacheable regions.
! 303: * These registers must be written as three separate bytes.
! 304: *
! 305: * NCRx+0: A31-A24 of starting address
! 306: * NCRx+1: A23-A16 of starting address
! 307: * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
! 308: *
! 309: * The non-cacheable region's starting address must be aligned to the
! 310: * size indicated by the NCR_SIZE_xx field.
! 311: */
! 312: #define NCR1 0xc4
! 313: #define NCR2 0xc7
! 314: #define NCR3 0xca
! 315: #define NCR4 0xcd
! 316:
! 317: #define NCR_SIZE_0K 0
! 318: #define NCR_SIZE_4K 1
! 319: #define NCR_SIZE_8K 2
! 320: #define NCR_SIZE_16K 3
! 321: #define NCR_SIZE_32K 4
! 322: #define NCR_SIZE_64K 5
! 323: #define NCR_SIZE_128K 6
! 324: #define NCR_SIZE_256K 7
! 325: #define NCR_SIZE_512K 8
! 326: #define NCR_SIZE_1M 9
! 327: #define NCR_SIZE_2M 10
! 328: #define NCR_SIZE_4M 11
! 329: #define NCR_SIZE_8M 12
! 330: #define NCR_SIZE_16M 13
! 331: #define NCR_SIZE_32M 14
! 332: #define NCR_SIZE_4G 15
! 333:
! 334: /*
! 335: * Performance monitor events.
! 336: *
! 337: * Note that 586-class and 686-class CPUs have different performance
! 338: * monitors available, and they are accessed differently:
! 339: *
! 340: * 686-class: `rdpmc' instruction
! 341: * 586-class: `rdmsr' instruction, CESR MSR
! 342: *
! 343: * The descriptions of these events are too lenghy to include here.
! 344: * See Appendix A of "Intel Architecture Software Developer's
! 345: * Manual, Volume 3: System Programming" for more information.
! 346: */
! 347:
! 348: /*
! 349: * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits
! 350: * is CTR1.
! 351: */
! 352:
! 353: #define PMC5_CESR_EVENT 0x003f
! 354: #define PMC5_CESR_OS 0x0040
! 355: #define PMC5_CESR_USR 0x0080
! 356: #define PMC5_CESR_E 0x0100
! 357: #define PMC5_CESR_P 0x0200
! 358:
! 359: /*
! 360: * 686-class Event Selector MSR format.
! 361: */
! 362:
! 363: #define PMC6_EVTSEL_EVENT 0x000000ff
! 364: #define PMC6_EVTSEL_UNIT 0x0000ff00
! 365: #define PMC6_EVTSEL_UNIT_SHIFT 8
! 366: #define PMC6_EVTSEL_USR (1 << 16)
! 367: #define PMC6_EVTSEL_OS (1 << 17)
! 368: #define PMC6_EVTSEL_E (1 << 18)
! 369: #define PMC6_EVTSEL_PC (1 << 19)
! 370: #define PMC6_EVTSEL_INT (1 << 20)
! 371: #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */
! 372: #define PMC6_EVTSEL_INV (1 << 23)
! 373: #define PMC6_EVTSEL_COUNTER_MASK 0xff000000
! 374: #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24
! 375:
! 376: /* Data Cache Unit */
! 377: #define PMC6_DATA_MEM_REFS 0x43
! 378: #define PMC6_DCU_LINES_IN 0x45
! 379: #define PMC6_DCU_M_LINES_IN 0x46
! 380: #define PMC6_DCU_M_LINES_OUT 0x47
! 381: #define PMC6_DCU_MISS_OUTSTANDING 0x48
! 382:
! 383: /* Instruction Fetch Unit */
! 384: #define PMC6_IFU_IFETCH 0x80
! 385: #define PMC6_IFU_IFETCH_MISS 0x81
! 386: #define PMC6_ITLB_MISS 0x85
! 387: #define PMC6_IFU_MEM_STALL 0x86
! 388: #define PMC6_ILD_STALL 0x87
! 389:
! 390: /* L2 Cache */
! 391: #define PMC6_L2_IFETCH 0x28
! 392: #define PMC6_L2_LD 0x29
! 393: #define PMC6_L2_ST 0x2a
! 394: #define PMC6_L2_LINES_IN 0x24
! 395: #define PMC6_L2_LINES_OUT 0x26
! 396: #define PMC6_L2_M_LINES_INM 0x25
! 397: #define PMC6_L2_M_LINES_OUTM 0x27
! 398: #define PMC6_L2_RQSTS 0x2e
! 399: #define PMC6_L2_ADS 0x21
! 400: #define PMC6_L2_DBUS_BUSY 0x22
! 401: #define PMC6_L2_DBUS_BUSY_RD 0x23
! 402:
! 403: /* External Bus Logic */
! 404: #define PMC6_BUS_DRDY_CLOCKS 0x62
! 405: #define PMC6_BUS_LOCK_CLOCKS 0x63
! 406: #define PMC6_BUS_REQ_OUTSTANDING 0x60
! 407: #define PMC6_BUS_TRAN_BRD 0x65
! 408: #define PMC6_BUS_TRAN_RFO 0x66
! 409: #define PMC6_BUS_TRANS_WB 0x67
! 410: #define PMC6_BUS_TRAN_IFETCH 0x68
! 411: #define PMC6_BUS_TRAN_INVAL 0x69
! 412: #define PMC6_BUS_TRAN_PWR 0x6a
! 413: #define PMC6_BUS_TRANS_P 0x6b
! 414: #define PMC6_BUS_TRANS_IO 0x6c
! 415: #define PMC6_BUS_TRAN_DEF 0x6d
! 416: #define PMC6_BUS_TRAN_BURST 0x6e
! 417: #define PMC6_BUS_TRAN_ANY 0x70
! 418: #define PMC6_BUS_TRAN_MEM 0x6f
! 419: #define PMC6_BUS_DATA_RCV 0x64
! 420: #define PMC6_BUS_BNR_DRV 0x61
! 421: #define PMC6_BUS_HIT_DRV 0x7a
! 422: #define PMC6_BUS_HITM_DRDV 0x7b
! 423: #define PMC6_BUS_SNOOP_STALL 0x7e
! 424:
! 425: /* Floating Point Unit */
! 426: #define PMC6_FLOPS 0xc1
! 427: #define PMC6_FP_COMP_OPS_EXE 0x10
! 428: #define PMC6_FP_ASSIST 0x11
! 429: #define PMC6_MUL 0x12
! 430: #define PMC6_DIV 0x12
! 431: #define PMC6_CYCLES_DIV_BUSY 0x14
! 432:
! 433: /* Memory Ordering */
! 434: #define PMC6_LD_BLOCKS 0x03
! 435: #define PMC6_SB_DRAINS 0x04
! 436: #define PMC6_MISALIGN_MEM_REF 0x05
! 437: #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */
! 438: #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */
! 439:
! 440: /* Instruction Decoding and Retirement */
! 441: #define PMC6_INST_RETIRED 0xc0
! 442: #define PMC6_UOPS_RETIRED 0xc2
! 443: #define PMC6_INST_DECODED 0xd0
! 444: #define PMC6_EMON_KNI_INST_RETIRED 0xd8
! 445: #define PMC6_EMON_KNI_COMP_INST_RET 0xd9
! 446:
! 447: /* Interrupts */
! 448: #define PMC6_HW_INT_RX 0xc8
! 449: #define PMC6_CYCLES_INT_MASKED 0xc6
! 450: #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
! 451:
! 452: /* Branches */
! 453: #define PMC6_BR_INST_RETIRED 0xc4
! 454: #define PMC6_BR_MISS_PRED_RETIRED 0xc5
! 455: #define PMC6_BR_TAKEN_RETIRED 0xc9
! 456: #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
! 457: #define PMC6_BR_INST_DECODED 0xe0
! 458: #define PMC6_BTB_MISSES 0xe2
! 459: #define PMC6_BR_BOGUS 0xe4
! 460: #define PMC6_BACLEARS 0xe6
! 461:
! 462: /* Stalls */
! 463: #define PMC6_RESOURCE_STALLS 0xa2
! 464: #define PMC6_PARTIAL_RAT_STALLS 0xd2
! 465:
! 466: /* Segment Register Loads */
! 467: #define PMC6_SEGMENT_REG_LOADS 0x06
! 468:
! 469: /* Clocks */
! 470: #define PMC6_CPU_CLK_UNHALTED 0x79
! 471:
! 472: /* MMX Unit */
! 473: #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */
! 474: #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */
! 475: #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */
! 476: #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */
! 477: #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */
! 478: #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */
! 479: #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */
! 480:
! 481: /* Segment Register Renaming */
! 482: #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */
! 483: #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */
! 484: #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */
! 485:
! 486: /* VIA C3 crypto featureset: for i386_has_xcrypt */
! 487: #define C3_HAS_AES 1 /* cpu has AES */
! 488: #define C3_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
! 489: #define C3_HAS_MM 4 /* cpu has RSA instructions */
! 490: #define C3_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
! 491:
! 492: /* Centaur Extended Feature flags */
! 493: #define C3_CPUID_HAS_RNG 0x000004
! 494: #define C3_CPUID_DO_RNG 0x000008
! 495: #define C3_CPUID_HAS_ACE 0x000040
! 496: #define C3_CPUID_DO_ACE 0x000080
! 497: #define C3_CPUID_HAS_ACE2 0x000100
! 498: #define C3_CPUID_DO_ACE2 0x000200
! 499: #define C3_CPUID_HAS_PHE 0x000400
! 500: #define C3_CPUID_DO_PHE 0x000800
! 501: #define C3_CPUID_HAS_PMM 0x001000
! 502: #define C3_CPUID_DO_PMM 0x002000
! 503:
! 504: /* VIA C3 xcrypt-* instruction context control options */
! 505: #define C3_CRYPT_CWLO_ROUND_M 0x0000000f
! 506: #define C3_CRYPT_CWLO_ALG_M 0x00000070
! 507: #define C3_CRYPT_CWLO_ALG_AES 0x00000000
! 508: #define C3_CRYPT_CWLO_KEYGEN_M 0x00000080
! 509: #define C3_CRYPT_CWLO_KEYGEN_HW 0x00000000
! 510: #define C3_CRYPT_CWLO_KEYGEN_SW 0x00000080
! 511: #define C3_CRYPT_CWLO_NORMAL 0x00000000
! 512: #define C3_CRYPT_CWLO_INTERMEDIATE 0x00000100
! 513: #define C3_CRYPT_CWLO_ENCRYPT 0x00000000
! 514: #define C3_CRYPT_CWLO_DECRYPT 0x00000200
! 515: #define C3_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
! 516: #define C3_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
! 517: #define C3_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
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