Annotation of sys/arch/i386/include/pctr.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: pctr.h,v 1.12 2003/05/27 23:52:01 fgsch Exp $ */
2:
3: /*
4: * Pentium performance counter driver for OpenBSD.
5: * Copyright 1996 David Mazieres <dm@lcs.mit.edu>.
6: *
7: * Modification and redistribution in source and binary forms is
8: * permitted provided that due credit is given to the author and the
9: * OpenBSD project by leaving this copyright notice intact.
10: */
11:
12: #ifndef _I386_PCTR_H_
13: #define _I386_PCTR_H_
14:
15: #include <sys/ioccom.h>
16:
17: typedef u_quad_t pctrval;
18:
19: #define PCTR_NUM 2
20:
21: struct pctrst {
22: u_int pctr_fn[PCTR_NUM]; /* Current settings of hardware counters */
23: pctrval pctr_tsc; /* Free-running 64-bit cycle counter */
24: pctrval pctr_hwc[PCTR_NUM]; /* Values of the hardware counters */
25: pctrval pctr_idl; /* Iterations of the idle loop */
26: };
27:
28: /* Bit values in fn fields and PIOCS ioctl's */
29: #define P5CTR_K 0x40 /* Monitor kernel-level events */
30: #define P5CTR_U 0x80 /* Monitor user-level events */
31: #define P5CTR_C 0x100 /* count cycles rather than events */
32:
33: #define P6CTR_U 0x010000 /* Monitor user-level events */
34: #define P6CTR_K 0x020000 /* Monitor kernel-level events */
35: #define P6CTR_E 0x040000 /* Edge detect */
36: #define P6CTR_EN 0x400000 /* Enable counters (counter 0 only) */
37: #define P6CTR_I 0x800000 /* Invert counter mask */
38:
39: /* Unit Mask bits */
40: #define P6CTR_UM_M 0x0800 /* Modified cache lines */
41: #define P6CTR_UM_E 0x0400 /* Exclusive cache lines */
42: #define P6CTR_UM_S 0x0200 /* Shared cache lines */
43: #define P6CTR_UM_I 0x0100 /* Invalid cache lines */
44: #define P6CTR_UM_MESI (P6CTR_UM_M|P6CTR_UM_E|P6CTR_UM_S|P6CTR_UM_I)
45: #define P6CTR_UM_A 0x2000 /* Any initiator (as opposed to self) */
46:
47: #define P6CTR_CM_SHIFT 24 /* Left shift for counter mask */
48:
49: /* ioctl to set which counter a device tracks. */
50: #define PCIOCRD _IOR('c', 1, struct pctrst) /* Read counter value */
51: #define PCIOCS0 _IOW('c', 8, unsigned int) /* Set counter 0 function */
52: #define PCIOCS1 _IOW('c', 9, unsigned int) /* Set counter 1 function */
53:
54: #define _PATH_PCTR "/dev/pctr"
55:
56: #define rdtsc() \
57: ({ \
58: pctrval v; \
59: __asm __volatile ("rdtsc" : "=A" (v)); \
60: v; \
61: })
62:
63: /* Read the performance counters (Pentium Pro only) */
64: #define rdpmc(ctr) \
65: ({ \
66: pctrval v; \
67: __asm __volatile ("rdpmc\n" \
68: "\tandl $0xff, %%edx" \
69: : "=A" (v) : "c" (ctr)); \
70: v; \
71: })
72:
73: #ifdef _KERNEL
74:
75: #define rdmsr(msr) \
76: ({ \
77: pctrval v; \
78: __asm __volatile ("rdmsr" : "=A" (v) : "c" (msr)); \
79: v; \
80: })
81:
82: #define wrmsr(msr, v) \
83: __asm __volatile ("wrmsr" :: "A" ((u_quad_t) (v)), "c" (msr));
84:
85: #endif /* _KERNEL */
86: #endif /* ! _I386_PCTR_H_ */
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