Annotation of sys/arch/hppa64/dev/elroyreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: elroyreg.h,v 1.1 2005/04/01 10:40:47 mickey Exp $ */
2:
3: /*
4: * Copyright (c) 2005 Michael Shalayeff
5: * All rights reserved.
6: *
7: * Permission to use, copy, modify, and distribute this software for any
8: * purpose with or without fee is hereby granted, provided that the above
9: * copyright notice and this permission notice appear in all copies.
10: *
11: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15: * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
16: * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
17: * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18: */
19:
20: struct elroy_regs {
21: /* std PCI bridge header */
22: u_int32_t pci_id; /* 0x000 rw PCI_ID */
23: u_int32_t pci_cmdstat; /* 0x004 rw PCI_COMMAND_STATUS_REG */
24: u_int32_t pci_class; /* 0x008 ro PCI_CLASS_REG */
25: u_int32_t pci_bhlc; /* 0x00c rw PCI_BHLC_REG */
26: u_int32_t res0[0x30/4]; /* 0x010 */
27:
28: /* HW Bridge registers */
29: u_int32_t pci_conf_addr; /* 0x040 rw config space address */
30: u_int32_t pad040;
31: u_int32_t pci_conf_data; /* 0x048 rw config space data */
32: u_int32_t pad048;
33: u_int64_t elroy_mtlt; /* 0x050 */
34: u_int32_t busnum; /* 0x058 bus number/scratch */
35: u_int32_t par058;
36: u_int64_t res1; /* 0x060 */
37: u_int64_t rope; /* 0x068 rope parity, loopback */
38: u_int64_t err_addr; /* 0x070 error log: address */
39: u_int64_t suspend; /* 0x078 rw suspend control */
40: u_int32_t arb_mask; /* 0x080 rw arbitration mask */
41: u_int32_t pad080;
42: #define ELROY_ARB_ENABLE 0x01 /* enable arbitration */
43: #define ELROY_ARB_PCIDEVA 0x02 /* PCI device A allow */
44: #define ELROY_ARB_PCIDEVB 0x04 /* PCI device A allow */
45: #define ELROY_ARB_PCIDEVC 0x08 /* PCI device A allow */
46: #define ELROY_ARB_PCIDEVD 0x10 /* PCI device A allow */
47: #define ELROY_ARB_PCIDEVE 0x20 /* PCI device A allow */
48: #define ELROY_ARB_PCIDEVF 0x40 /* PCI device A allow */
49: #define ELROY_ARB_PCIDEVG 0x80 /* PCI device A allow */
50: u_int64_t arb_pri; /* 0x088 arbitration priority */
51: u_int64_t arb_mode; /* 0x090 arbitration mode */
52: u_int64_t mtlt; /* 0x098 */
53: u_int64_t res2[12]; /* 0x0a0 */
54: u_int64_t mod_info; /* 0x100 */
55: u_int32_t control; /* 0x108 */
56: #define ELROY_CONTROL_RF 0x01 /* reset pci */
57: #define ELROY_CONTROL_VE 0x08 /* VGA enable */
58: #define ELROY_CONTROL_CL 0x10 /* clear error log */
59: #define ELROY_CONTROL_CE 0x20 /* clear error log enable */
60: #define ELROY_CONTROL_HF 0x40 /* hard fail enable */
61: u_int32_t status; /* 0x10c */
62: #define ELROY_STATUS_RC 0x01 /* reset complete */
63: #define ELROY_STATUS_BITS "\020\01RC"
64: u_int64_t res3[30]; /* 0x110 */
65: u_int64_t lmmio_base; /* 0x200 */
66: u_int64_t lmmio_mask; /* 0x208 */
67: u_int64_t gmmio_base; /* 0x210 */
68: u_int64_t gmmio_mask; /* 0x218 */
69: u_int64_t wlmmio_base; /* 0x220 */
70: u_int64_t wlmmio_mask; /* 0x228 */
71: u_int64_t wgmmio_base; /* 0x230 */
72: u_int64_t wgmmio_mask; /* 0x238 */
73: u_int32_t io_base; /* 0x240 */
74: u_int32_t pad240;
75: u_int32_t io_mask; /* 0x248 */
76: u_int32_t pad248;
77: u_int32_t res4[4]; /* 0x250 */
78: u_int32_t eio_base; /* 0x260 */
79: u_int32_t pad260;
80: u_int32_t eio_mask; /* 0x268 */
81: u_int32_t pad268;
82: #define ELROY_BASE_RE 0x01 /* range enable */
83: u_int64_t res5; /* 0x270 */
84: u_int64_t dmac_ctrl; /* 0x278 DMA connection control */
85: u_int64_t res6[16]; /* 0x280 */
86: u_int64_t ibase; /* 0x300 */
87: u_int64_t imask; /* 0x308 */
88: u_int64_t hint_cfg; /* 0x310 */
89: u_int64_t res7[13]; /* 0x318 */
90: u_int64_t hints[14]; /* 0x380 */
91: u_int64_t res8[2]; /* 0x3f0 */
92: u_int64_t res9[64]; /* 0x400 */
93: u_int64_t pad0; /* 0x600 */
94: u_int64_t pci_drive; /* 0x608 */
95: u_int64_t rope_cfg; /* 0x610 */
96: u_int64_t clk_ctl; /* 0x618 */
97: u_int32_t pad1; /* 0x620 */
98: u_int32_t res10[23]; /* 0x624 */
99: u_int32_t err_cfg; /* 0x680 error config */
100: u_int32_t pad680;
101: #define ELROY_ERRCFG_PW 0x01 /* PIO writes parity errors */
102: #define ELROY_ERRCFG_PR 0x02 /* PIO reads parity errors */
103: #define ELROY_ERRCFG_DW 0x04 /* DMA writes parity errors */
104: #define ELROY_ERRCFG_DR 0x08 /* DMA reads parity errors */
105: #define ELROY_ERRCFG_CM 0x10 /* no fatal on config space */
106: #define ELROY_ERRCFG_SMART 0x20 /* smart bus mode */
107: u_int64_t err_stat; /* 0x688 error status */
108: u_int64_t err_mid; /* 0x690 error log: master id */
109: u_int64_t rope_estat; /* 0x698 rope error status */
110: u_int64_t rope_eclr; /* 0x6a0 rope error clear */
111: u_int64_t res11[42]; /* 0x6a8 */
112: u_int64_t regbus; /* 0x7f8 reads 0x3ff */
113: u_int32_t apic_addr; /* 0x800 APIC address register */
114: u_int32_t pad800;
115: u_int64_t res12;
116: u_int32_t apic_data; /* 0x810 APIC data register */
117: u_int32_t pad808;
118: u_int64_t res13[5];
119: u_int32_t apic_eoi; /* 0x840 APIC interrupt ack */
120: u_int32_t pad840;
121: u_int32_t apic_softint; /* 0x850 write generates softint */
122: u_int32_t pad850;
123: u_int64_t res14[123]; /* 0x858 */
124: /*0x1000 */
125: } __packed;
126:
127: /* APIC registers */
128: #define APIC_VERSION 0x01
129: #define APIC_VERSION_MASK 0xff
130: #define APIC_VERSION_NENT 0xff0000
131: #define APIC_VERSION_NENT_SHIFT 16
132: #define APIC_ENT0(i) (0x10 + (i)*2)
133: #define APIC_ENT0_VEC 0x000ff
134: #define APIC_ENT0_MOD 0x00700 /* delivery mode */
135: #define APIC_ENT0_FXD 0x00000
136: #define APIC_ENT0_RDR 0x00100
137: #define APIC_ENT0_PMI 0x00200
138: #define APIC_ENT0_NMI 0x00400
139: #define APIC_ENT0_INI 0x00500
140: #define APIC_ENT0_EXT 0x00700
141: #define APIC_ENT0_PEND 0x01000 /* int is pending */
142: #define APIC_ENT0_LOW 0x02000 /* polarity */
143: #define APIC_ENT0_LEV 0x08000 /* edge/level */
144: #define APIC_ENT0_MASK 0x10000 /* mask int */
145: #define APIC_ENT1(i) (0x11 + (i)*2)
146:
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