Annotation of sys/arch/hppa/include/reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: reg.h,v 1.11 2004/04/07 18:24:19 mickey Exp $ */
2:
3: /*
4: * Copyright (c) 1998-2004 Michael Shalayeff
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19: * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22: * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25: * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26: * THE POSSIBILITY OF SUCH DAMAGE.
27: */
28: /*
29: * Copyright (c) 1990,1994 The University of Utah and
30: * the Computer Systems Laboratory at the University of Utah (CSL).
31: * All rights reserved.
32: *
33: * Permission to use, copy, modify and distribute this software is hereby
34: * granted provided that (1) source code retains these copyright, permission,
35: * and disclaimer notices, and (2) redistributions including binaries
36: * reproduce the notices in supporting documentation, and (3) all advertising
37: * materials mentioning features or use of this software display the following
38: * acknowledgement: ``This product includes software developed by the
39: * Computer Systems Laboratory at the University of Utah.''
40: *
41: * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
42: * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
43: * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
44: *
45: * CSL requests users of this software to return to csl-dist@cs.utah.edu any
46: * improvements that they make and grant CSL redistribution rights.
47: *
48: * Utah $Hdr: regs.h 1.6 94/12/14$
49: * Author: Bob Wheeler, University of Utah CSL
50: */
51:
52: #ifndef _MACHINE_REG_H_
53: #define _MACHINE_REG_H_
54:
55: /*
56: * constants for registers for use with the following routines:
57: *
58: * void mtctl(reg, value) - move to control register
59: * int mfctl(reg) - move from control register
60: * int mtsp(sreg, value) - move to space register
61: * int mfsr(sreg) - move from space register
62: */
63:
64: #define CR_RCTR 0
65: #define CR_PIDR1 8
66: #define CR_PIDR2 9
67: #define CR_CCR 10
68: #define CR_SAR 11
69: #define CR_PIDR3 12
70: #define CR_PIDR4 13
71: #define CR_IVA 14
72: #define CR_EIEM 15
73: #define CR_ITMR 16
74: #define CR_PCSQ 17
75: #define CR_PCOQ 18
76: #define CR_IIR 19
77: #define CR_ISR 20
78: #define CR_IOR 21
79: #define CR_IPSW 22
80: #define CR_EIRR 23
81: #define CR_HPTMASK 24
82: #define CR_VTOP 25
83: #define CR_TR2 26
84: #define CR_TR3 27
85: #define CR_HVTP 28 /* points to a faulted HVT slot on LC cpus */
86: #define CR_TR5 29
87: #define CR_UPADDR 30 /* paddr of U-area of curproc */
88: #define CR_TR7 31
89:
90: /*
91: * Diagnostic registers and bit positions
92: */
93: #define DR_CPUCFG 0
94:
95: #define DR0_PCXS_DHPMC 10 /* r/c D-cache error flag */
96: #define DR0_PCXS_ILPMC 14 /* r/c I-cache error flag */
97: #define DR0_PCXS_EQWSTO 16 /* r/w enable quad-word stores */
98: #define DR0_PCXS_IHE 18 /* r/w I-cache sid hash enable */
99: #define DR0_PCXS_DOMAIN 19
100: #define DR0_PCXS_DHE 20 /* r/w D-cache sid hash enable */
101:
102: #define DR0_PCXT_DHPMC 10 /* r/c L1 D-cache error flag */
103: #define DR0_PCXT_ILPMC 14 /* r/c L1 I-cache error flag */
104: #define DR0_PCXT_IHE 18 /* r/w I-cache sid hash enable */
105: #define DR0_PCXT_DHE 20 /* r/w D-cache sid hash enable */
106:
107: #define DR0_PCXL_L2IHPMC 6 /* r/c L2 I-cache error flag */
108: #define DR0_PCXL_L2IHPMC_DIS 7 /* r/w L2 I-cache hpmc disable mask */
109: #define DR0_PCXL_L2DHPMC 8 /* r/c L2 D-cache error flag */
110: #define DR0_PCXL_L2DHPMC_DIS 9 /* r/w L2 D-cache hpmc disable mask */
111: #define DR0_PCXL_L1IHPMC 10 /* r/c L1 I-cache error flag */
112: #define DR0_PCXL_L1IHPMC_DIS 11 /* r/w L1 I-cache hpmc disable mask */
113: #define DR0_PCXL_L2PARERR 15 /* r/c L2 Cache parity error (4 bit) */
114: #define DR0_PCXL_STORE0 16 /* r/w scratch space */
115: #define DR0_PCXL_PFMASK 17 /* r/w power-fail trap mask */
116: #define DR0_PCXL_STORE1 18 /* r/w scratch */
117: #define DR0_PCXL_FASTMODE 19 /* r 0-fast, 1-slow */
118: #define DR0_PCXL_ISTRM_EN 20 /* r/w I-cache streaming enable */
119: #define DR0_PCXL_DUAL_DIS 22 /* r/w disable dual-issue (2 bit) */
120: #define DR0_PCXL_ENDIAN 23 /* r/w little endian traps */
121: #define DR0_PCXL_SOU_EN 24 /* r/w stall-on-use on dc misses */
122: #define DR0_PCXL_SHINT_EN 25 /* r/w no-fill on miss store hints */
123: #define DR0_PCXL_IPREF_EN 26 /* r/w L2 to L1 I-cache prefetch */
124: #define DR0_PCXL_L2DHASH_EN 27 /* r/w L2 D-cache hash enable */
125: #define DR0_PCXL_L2IHASH_EN 28 /* r/w L2 I-cache hash enable */
126: #define DR0_PCXL_L1ICACHE_EN 29 /* r/w L1 I-cache enable */
127: #define DR0_PCXL_HIT 30 /* r Diag cache read hit indication */
128: #define DR0_PCXL_PARERR 31 /* r Diag cache read parity error */
129:
130: #define DR0_PCXL2_L1DHPMC 8 /* r/c L1 D-cache error flag */
131: #define DR0_PCXL2_L1DHPMC_DIS 9 /* r/w L1 D-cache hpmc disable */
132: #define DR0_PCXL2_L2DHPMC 10 /* r/c L1 I-cache error flag */
133: #define DR0_PCXL2_L2DHPMC_DIS 11 /* r/w L1 I-cache hpmc disable */
134: #define DR0_PCXL2_SCRATCH 12 /* r/w scratch register */
135: #define DR0_PCXL2_ACCEL_IO 13 /* /w enable accel IO writes */
136: #define DR0_PCXL2_STORE0 16 /* r/w scratch space */
137: #define DR0_PCXL2_PFMASK 17 /* r/w power-fail trap mask */
138: #define DR0_PCXL2_STORE1 18 /* r/w scratch */
139: #define DR0_PCXL2_DCSAFE 19 /* r/w serialize all data cache hangs */
140: #define DR0_PCXL2_ISTRM_EN 20 /* r/w I-cache streaming enable */
141: #define DR0_PCXL2_DUAL_DIS 22 /* r/w disable dual-issue (2 bit) */
142: #define DR0_PCXL2_ENDIAN 23 /* r/w little endian traps */
143: #define DR0_PCXL2_SOU_EN 24 /* r/w stall-on-use on dc misses */
144: #define DR0_PCXL2_SHINT_EN 25 /* r/w no-fill on miss store hints */
145: #define DR0_PCXL2_IPREF_EN 26 /* r/w L2 to L1 I-cache prefetch */
146: #define DR0_PCXL2_LMIN_EN 27 /* r/w minor ill insn traps on LIH */
147: #define DR0_PCXL2_RMIN_EN 28 /* r/w major ill insn traps on RIH */
148: #define DR0_PCXL2_L1CACHE_EN 29 /* r/w L1 I-cache enable */
149:
150: #define DR_DTLB 8
151:
152: #define DR_ITLB 9
153:
154: #define DR0_PCXL2_HTLB_ADDR 24 /* page address of the htlb */
155: #define DR0_PCXL2_HTLB_CFG 25 /* htlb config */
156: #define DR0_PCXL2_HTLB_P 0 /* r latches power fail signal */
157: #define DR0_PCXL2_HTLB_MASK 19 /* w 12bit mask of the hash */
158: #define DR0_PCXL2_HTLB_FP 26 /* r/w 3bit FP delay */
159: #define DR0_PCXL2_HTLB_I 28 /* r/w disable ITLB htlb lookup */
160: #define DR0_PCXL2_HTLB_U 29 /* r/w set cr28 only if tag nomatch */
161: #define DR0_PCXL2_HTLB_N 30 /* r/w set cr28 from w3 or w7 (0) */
162: #define DR0_PCXL2_HTLB_D 31 /* r/w disable DTLB htlb lookup */
163:
164: #define DR_ITLB_SIZE_1 24
165: #define DR_ITLB_SIZE_0 25
166:
167: #define DR_DTLB_SIZE_1 26
168: #define DR_DTLB_SIZE_0 27
169:
170: #define CCR_MASK 0xff
171:
172: #define HPPA_NREGS (32)
173: #define HPPA_NFPREGS (33) /* 33rd is used for r0 in fpemul */
174:
175: #ifndef _LOCORE
176:
177: struct reg {
178: u_int32_t r_regs[HPPA_NREGS]; /* r0 is sar */
179: u_int32_t r_pc;
180: u_int32_t r_npc;
181: };
182:
183: struct fpreg {
184: u_int64_t fpr_regs[HPPA_NFPREGS];
185: };
186: #endif /* !_LOCORE */
187:
188: #endif /* _MACHINE_REG_H_ */
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