Annotation of sys/arch/hppa/include/pdc.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: pdc.h,v 1.35 2007/07/15 20:03:48 kettenis Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 1990 mt Xinu, Inc. All rights reserved.
! 5: * Copyright (c) 1990,1991,1992,1994 University of Utah. All rights reserved.
! 6: *
! 7: * Permission to use, copy, modify and distribute this software is hereby
! 8: * granted provided that (1) source code retains these copyright, permission,
! 9: * and disclaimer notices, and (2) redistributions including binaries
! 10: * reproduce the notices in supporting documentation, and (3) all advertising
! 11: * materials mentioning features or use of this software display the following
! 12: * acknowledgement: ``This product includes software developed by the
! 13: * Computer Systems Laboratory at the University of Utah.''
! 14: *
! 15: * Copyright (c) 1990 mt Xinu, Inc.
! 16: * This file may be freely distributed in any form as long as
! 17: * this copyright notice is included.
! 18: * MTXINU, THE UNIVERSITY OF UTAH, AND CSL PROVIDE THIS SOFTWARE ``AS
! 19: * IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
! 20: * WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
! 21: * FITNESS FOR A PARTICULAR PURPOSE.
! 22: *
! 23: * CSL requests users of this software to return to csl-dist@cs.utah.edu any
! 24: * improvements that they make and grant CSL redistribution rights.
! 25: *
! 26: * Utah $Hdr: pdc.h 1.12 94/12/14$
! 27: * Author: Jeff Forys (CSS), Dave Slattengren (mtXinu)
! 28: */
! 29:
! 30: #ifndef _MACHINE_PDC_H_
! 31: #define _MACHINE_PDC_H_
! 32:
! 33: /*
! 34: * Definitions for interaction with "Processor Dependent Code",
! 35: * which is a set of ROM routines used to provide information to the OS.
! 36: * Also includes definitions for the layout of "Page Zero" memory when
! 37: * boot code is invoked.
! 38: *
! 39: * Glossary:
! 40: * PDC: Processor Dependent Code (ROM or copy of ROM).
! 41: * IODC: I/O Dependent Code (module-type dependent code).
! 42: * IPL: Boot program (loaded into memory from boot device).
! 43: * HPA: Hard Physical Address (hardwired address).
! 44: * SPA: Soft Physical Address (reconfigurable address).
! 45: *
! 46: *
! 47: *
! 48: *
! 49: * Definitions for talking to IODC (I/O Dependent Code).
! 50: *
! 51: * The PDC is used to load I/O Dependent Code from a particular module.
! 52: * I/O Dependent Code is module-type dependent software which provides
! 53: * a uniform way to identify, initialize, and access a module (and in
! 54: * some cases, their devices).
! 55: */
! 56:
! 57: /*
! 58: * Our Initial Memory Module is laid out as follows.
! 59: *
! 60: * 0x000 +--------------------+
! 61: * | Page Zero (iomod.h)|
! 62: * 0x800 +--------------------+
! 63: * | |
! 64: * | |
! 65: * | PDC |
! 66: * | |
! 67: * | |
! 68: * MEM_FREE +--------------------+
! 69: * | |
! 70: * | Console IODC |
! 71: * | |
! 72: * MEM_FREE+64k +--------------------+
! 73: * | |
! 74: * | Boot Device IODC |
! 75: * | |
! 76: * IPL_START +--------------------+
! 77: * | |
! 78: * | IPL Code or Kernel |
! 79: * | |
! 80: * +--------------------+
! 81: *
! 82: * Restrictions:
! 83: * MEM_FREE (pagezero.mem_free) can be no greater than 32K.
! 84: * The PDC may use up to MEM_FREE + 32K (for Console & Boot IODC).
! 85: * IPL_START must be less than or equal to 64K.
! 86: *
! 87: * The IPL (boot) Code is immediately relocated to RELOC (check
! 88: * "../stand/Makefile") to make way for the Kernel.
! 89: */
! 90:
! 91: #define IODC_MAXSIZE (16 * 4 * 1024) /* maximum size of IODC */
! 92: #define IODC_MINIOSIZ 64 /* minimum buffer size for IODC call */
! 93: #define IODC_MAXIOSIZ (64 * 1024) /* maximum buffer size for IODC call */
! 94: #define IODC_IOSIZ (16 * 1024)
! 95:
! 96: #define PDC_ALIGNMENT __attribute__ ((__aligned__(64)))
! 97: #define PDC_STACKSIZE (4*NBPG)
! 98:
! 99: /*
! 100: * The PDC Entry Points and their arguments...
! 101: */
! 102:
! 103: #define PDC_POW_FAIL 1 /* prepare for power failure */
! 104: #define PDC_POW_FAIL_DFLT 0
! 105:
! 106: #define PDC_CHASSIS 2 /* update chassis display (see below) */
! 107: #define PDC_CHASSIS_DISP 0 /* update display */
! 108: #define PDC_CHASSIS_WARN 1 /* return warnings */
! 109: #define PDC_CHASSIS_ALL 2 /* update display & return warnings */
! 110: #define PDC_CHASSIS_INFO 128 /* return led/lcd info */
! 111:
! 112: #define PDC_PIM 3 /* access Processor Internal Memory */
! 113: #define PDC_PIM_HPMC 0 /* read High Pri Mach Chk data */
! 114: #define PDC_PIM_SIZE 1 /* return size */
! 115: #define PDC_PIM_LPMC 2 /* read Low Pri Mach Chk data */
! 116: #define PDC_PIM_SBD 3 /* read soft boot data */
! 117: #define PDC_PIM_TOC 4 /* read TOC data (used to use HPMC) */
! 118:
! 119: #define PDC_MODEL 4 /* processor model number info */
! 120: #define PDC_MODEL_INFO 0 /* processor model number info */
! 121: #define PDC_MODEL_BOOTID 1 /* set BOOT_ID of processor */
! 122: #define PDC_MODEL_COMP 2 /* return component version numbers */
! 123: #define PDC_MODEL_MODEL 3 /* return system model information */
! 124: #define PDC_MODEL_ENSPEC 4 /* enable product-specific instrs */
! 125: #define PDC_MODEL_DISPEC 5 /* disable product-specific instrs */
! 126: #define PDC_MODEL_CPUID 6 /* return CPU versions */
! 127: #define PDC_MODEL_CPBALITIES 7 /* return capabilites */
! 128: #define PDC_MODEL_GETBOOTOPTS 8 /* return boot test options */
! 129: #define PDC_MODEL_SETBOOTOPTS 9 /* set boot test options */
! 130:
! 131: #define PDC_CACHE 5 /* return cache and TLB params */
! 132: #define PDC_CACHE_DFLT 0 /* return parameters */
! 133: #define PDC_CACHE_SETCS 1 /* set coherence state */
! 134: #define PDC_CACHE_GETSPIDB 2 /* get space-id bits */
! 135:
! 136: #define PDC_HPA 6 /* return HPA of processor */
! 137: #define PDC_HPA_DFLT 0
! 138: #define PDC_HPA_MODULES 1
! 139:
! 140: #define PDC_COPROC 7 /* return co-processor configuration */
! 141: #define PDC_COPROC_DFLT 0
! 142:
! 143: #define PDC_IODC 8 /* talk to IODC */
! 144: #define PDC_IODC_READ 0 /* read IODC entry point */
! 145: #define IODC_DATA 0 /* get first 16 bytes from mod IODC */
! 146: #define IODC_INIT 3 /* initialize (see options below) */
! 147: #define IODC_INIT_FIRST 2 /* find first device on module */
! 148: #define IODC_INIT_NEXT 3 /* find subsequent devices on module */
! 149: #define IODC_INIT_ALL 4 /* initialize module and device */
! 150: #define IODC_INIT_DEV 5 /* initialize device */
! 151: #define IODC_INIT_MOD 6 /* initialize module */
! 152: #define IODC_INIT_MSG 9 /* return error message(s) */
! 153: #define IODC_INIT_STR 20 /* find device w/ spec in string */
! 154: #define IODC_IO 4 /* perform I/O (see options below) */
! 155: #define IODC_IO_READ 0 /* read from boot device */
! 156: #define IODC_IO_WRITE 1 /* write to boot device */
! 157: #define IODC_IO_CONSIN 2 /* read from console */
! 158: #define IODC_IO_CONSOUT 3 /* write to conosle */
! 159: #define IODC_IO_CLOSE 4 /* close device */
! 160: #define IODC_IO_MSG 9 /* return error message(s) */
! 161: #define IODC_SPA 5 /* get extended SPA information */
! 162: #define IODC_SPA_DFLT 0 /* return SPA information */
! 163: #define IODC_TEST 8 /* perform self tests */
! 164: #define IODC_TEST_INFO 0 /* return test information */
! 165: #define IODC_TEST_STEP 1 /* execute a particular test */
! 166: #define IODC_TEST_TEST 2 /* describe a test section */
! 167: #define IODC_TEST_MSG 9 /* return error message(s) */
! 168: #define PDC_IODC_NINIT 2 /* non-destructive init */
! 169: #define PDC_IODC_DINIT 3 /* destructive init */
! 170: #define PDC_IODC_MEMERR 4 /* check for memory errors */
! 171: #define PDC_IODC_IMEMMASTER 5 /* interlieved memory master ID */
! 172:
! 173: #define PDC_TOD 9 /* access time-of-day clock */
! 174: #define PDC_TOD_READ 0 /* read TOD clock */
! 175: #define PDC_TOD_WRITE 1 /* write TOD clock */
! 176: #define PDC_TOD_ITIMER 2 /* calibrate Interval Timer (CR16) */
! 177:
! 178: #define PDC_STABLE 10 /* access Stable Storage (SS) */
! 179: #define PDC_STABLE_READ 0 /* read SS */
! 180: #define PDC_STABLE_WRITE 1 /* write SS */
! 181: #define PDC_STABLE_SIZE 2 /* return size of SS */
! 182: #define PDC_STABLE_VRFY 3 /* verify contents of SS */
! 183: #define PDC_STABLE_INIT 4 /* initialize SS */
! 184:
! 185: #define PDC_NVM 11 /* access Non-Volatile Memory (NVM) */
! 186: #define PDC_NVM_READ 0 /* read NVM */
! 187: #define PDC_NVM_WRITE 1 /* write NVM */
! 188: #define PDC_NVM_SIZE 2 /* return size of NVM */
! 189: #define PDC_NVM_VRFY 3 /* verify contents of NVM */
! 190: #define PDC_NVM_INIT 4 /* initialize NVM */
! 191:
! 192: #define PDC_ADD_VALID 12 /* check address for validity */
! 193: #define PDC_ADD_VALID_DFLT 0
! 194:
! 195: #define PDC_BUS_BAD 13 /* verify Error Detection Circuitry (EDC) */
! 196: #define PDC_BUS_BAD_DLFT 0
! 197:
! 198: #define PDC_DEBUG 14 /* return address of PDC debugger */
! 199: #define PDC_DEBUG_DFLT 0
! 200:
! 201: #define PDC_INSTR 15 /* return instr that invokes PDCE_CHECK */
! 202: #define PDC_INSTR_DFLT 0
! 203:
! 204: #define PDC_PROC 16 /* stop currently executing processor */
! 205: #define PDC_PROC_STOP 0
! 206: #define PDC_PROC_RENDEZVOUS 1
! 207:
! 208: #define PDC_CONF 17 /* (de)configure a module */
! 209: #define PDC_CONF_DECONF 0 /* deconfigure module */
! 210: #define PDC_CONF_RECONF 1 /* reconfigure module */
! 211: #define PDC_CONF_INFO 2 /* get config informaion */
! 212:
! 213: #define PDC_BLOCK_TLB 18 /* Manage Block TLB entries (BTLB) */
! 214: #define PDC_BTLB_DEFAULT 0 /* Return BTLB configuration info */
! 215: #define PDC_BTLB_INSERT 1 /* Insert a BTLB entry */
! 216: #define PDC_BTLB_PURGE 2 /* Purge a BTLB entry */
! 217: #define PDC_BTLB_PURGE_ALL 3 /* Purge all BTLB entries */
! 218:
! 219: #define PDC_TLB 19 /* Manage Hardware TLB handling */
! 220: #define PDC_TLB_INFO 0 /* Return HW-TLB configuration info */
! 221: #define PDC_TLB_CONFIG 1 /* Set HW-TLB pdir base and size */
! 222:
! 223: #define PDC_TLB_CURRPDE 1 /* cr28 points to current pde on miss */
! 224: #define PDC_TLB_RESERVD 3 /* reserved */
! 225: #define PDC_TLB_NEXTPDE 5 /* cr28 points to next pde on miss */
! 226: #define PDC_TLB_WORD3 7 /* cr28 is word 3 of 16 byte pde */
! 227:
! 228: #define PDC_PSW 21 /* manage default values of configurable psw bits */
! 229: #define PDC_PSW_GETMASK 0 /* get mask */
! 230: #define PDC_PSW_DEFAULTS 1 /* get default bits values */
! 231: #define PDC_PSW_SETDEFAULTS 2 /* set default bits values */
! 232:
! 233: #define PDC_SYSMAP 22 /* map system modules */
! 234: #define PDC_SYSMAP_FIND 0 /* find module by index */
! 235: #define PDC_SYSMAP_ADDR 1 /* fetch list of addresses */
! 236: #define PDC_SYSMAP_HPA 2 /* get hpa from devpath */
! 237:
! 238: #define PDC_SOFT_POWER 23 /* support for soft power switch */
! 239: #define PDC_SOFT_POWER_INFO 0 /* get info about soft power switch */
! 240: #define PDC_SOFT_POWER_ENABLE 1 /* enable/disable soft power switch */
! 241:
! 242: #define PDC_PAT_CELL 64 /* cell operations */
! 243: #define PDC_PAT_CELL_GETID 0 /* get cell id number */
! 244: #define PDC_PAT_CELL_GETINFO 1 /* get cell info */
! 245: #define PDC_PAT_CELL_MODULE 2 /* get module info */
! 246: #define PDC_PAT_IOVIEW 0
! 247: #define PDC_PAT_PAVIEW 1
! 248:
! 249: #define PDC_PAT_CHASSIS 65 /* chassis log ops */
! 250: #define PDC_PAT_CHASSIS_WRITE 0
! 251: #define PDC_PAT_CHASSIS_READ 1
! 252:
! 253: #define PDC_PAT_CPU 67
! 254:
! 255: #define PDC_PAT_EVENT 68
! 256:
! 257: #define PDC_PAT_HPMC 70
! 258:
! 259: #define PDC_PAT_IO 71 /* online services for IO modules */
! 260: #define PDC_PAT_IO_GET_PCI_RTSZ 15
! 261: #define PDC_PAT_IO_GET_PCI_RT 16
! 262:
! 263: #define PDC_PAT_MEM 72
! 264:
! 265: #define PDC_PAT_NVRAM 73
! 266:
! 267: #define PDC_PAT_PROTDOM 74
! 268:
! 269: #define PDC_MEMMAP 128 /* hp700: return page information */
! 270: #define PDC_MEMMAP_HPA 0 /* map module # to HPA */
! 271:
! 272: #define PDC_EEPROM 129 /* Hversion dependent */
! 273: #define PDC_EEPROM_READ_WORD 0
! 274: #define PDC_EEPROM_WRITE_WORD 1
! 275: #define PDC_EEPROM_READ_BYTE 2
! 276: #define PDC_EEPROM_WRITE_BYTE 3
! 277:
! 278: #define PDC_IO 135
! 279: #define PDC_IO_READ_AND_CLEAR_ERRORS 0
! 280: #define PDC_IO_RESET 1
! 281: #define PDC_IO_RESET_DEVICES 2
! 282:
! 283: #define PDC_BROADCAST_RESET 136
! 284: #define PDC_DO_RESET 0
! 285: #define PDC_DO_FIRM_TEST_RESET 1
! 286: #define PDC_BR_RECONFIGURATION 2
! 287:
! 288: #define PDC_LAN_STATION_ID 138 /* Hversion dependent mechanism for */
! 289: #define PDC_LAN_STATION_ID_READ 0 /* getting the lan station address */
! 290:
! 291: #define PDC_PCI_INDEX 147 /* PCI rt access */
! 292: #define PDC_PCI_GET_INT_TBL_SZ 13
! 293: #define PDC_PCI_GET_INT_TBL 14
! 294:
! 295: #define PDC_ERR_OK 0 /* operation complete */
! 296: #define PDC_ERR_WARNING 3 /* OK, but warning */
! 297: #define PDC_ERR_NOPROC -1 /* no such procedure */
! 298: #define PDC_ERR_NOPT -2 /* no such option */
! 299: #define PDC_ERR_COMPL -3 /* unable to complete w/o error */
! 300: #define PDC_ERR_EOD -9 /* end of device list */
! 301: #define PDC_ERR_INVAL -10 /* invalid argument */
! 302: #define PDC_ERR_PFAIL -12 /* aborted by powerfail */
! 303:
! 304: #if !defined(_LOCORE)
! 305:
! 306: struct iomod;
! 307:
! 308: typedef int (*pdcio_t)(int, int, ...);
! 309: typedef int (*iodcio_t)(u_int, int, ...);
! 310:
! 311: /*
! 312: * Commonly used PDC calls and the structures they return.
! 313: */
! 314:
! 315: /*
! 316: * Device path specifications used by PDC.
! 317: */
! 318: struct device_path {
! 319: u_char dp_flags; /* see bit definitions below */
! 320: char dp_bc[6]; /* Bus Converter routing info to a specific */
! 321: /* I/O adaptor (< 0 means none, > 63 resvd) */
! 322: u_char dp_mod; /* fixed field of specified module */
! 323: int dp_layers[6]; /* device-specific info (ctlr #, unit # ...) */
! 324: };
! 325:
! 326: struct pdc_model { /* PDC_MODEL */
! 327: u_int hvers; /* hardware version */
! 328: u_int rev : 4; /* zero for all native processors */
! 329: u_int model : 20; /* 4 for all native processors */
! 330: u_int sh : 1; /* shadow registers are present */
! 331: u_int reserved : 2; /* reserved */
! 332: u_int mc : 1; /* module category (A - 0, B - 1) */
! 333: u_int reserved1 : 2; /* reserved */
! 334: u_int pa_lvl : 2; /* PA-RISC level */
! 335: u_int hw_id; /* unique processor hardware identifier */
! 336: u_int boot_id; /* same as hw_id */
! 337: u_int sw_id; /* software security and licensing */
! 338: u_int sw_cap; /* OS capabilities of processor */
! 339: u_int arch_rev; /* architecture revision */
! 340: u_int pot_key; /* potential key */
! 341: u_int curr_key; /* current key */
! 342: int filler1;
! 343: u_int filler2[22];
! 344: };
! 345:
! 346: struct pdc_cpuid { /* PDC_MODEL_CPUID */
! 347: u_int reserved : 20;
! 348: u_int version : 7; /* CPU version */
! 349: u_int revision : 5; /* CPU revision */
! 350: u_int filler[31];
! 351: };
! 352:
! 353: struct pdc_getbootopts { /* PDC_MODEL_GETBOOTOPTS */
! 354: u_int cur_test; /* current enabled tests */
! 355: u_int sup_test; /* supported tests */
! 356: u_int def_test; /* default enabled tests */
! 357: u_int filler[29];
! 358: };
! 359:
! 360: struct cache_cf { /* PDC_CACHE (for "struct pdc_cache") */
! 361: u_int cc_alias: 4, /* virtual address aliasing boundary */
! 362: cc_block: 4, /* used to determine most efficient stride */
! 363: cc_line : 3, /* max data written by store (16-byte mults) */
! 364: cc_resv1: 2, /* (reserved) */
! 365: cc_wt : 1, /* D-cache: write-to = 0, write-through = 1 */
! 366: cc_sh : 2, /* separate I and D = 0, shared I and D = 1 */
! 367: cc_cst : 3, /* D-cache: incoherent = 0, coherent = 1 */
! 368: cc_resv2:11, /* (reserved) */
! 369: cc_hvers: 2; /* H-VERSION dependent */
! 370: };
! 371:
! 372: struct tlb_cf { /* PDC_CACHE (for "struct pdc_cache") */
! 373: u_int tc_resv1:12, /* (reserved) */
! 374: tc_sh : 2, /* separate I and D = 0, shared I and D = 1 */
! 375: tc_hvers: 1, /* H-VERSION dependent */
! 376: tc_page : 1, /* 2K page size = 0, 4k page size = 1 */
! 377: tc_cst : 3, /* incoherent = 0, coherent = 1 */
! 378: tc_resv2: 5, /* (reserved) */
! 379: tc_assoc: 8; /* associativity of TLB */
! 380: };
! 381:
! 382: struct pdc_cache { /* PDC_CACHE */
! 383: /* Instruction cache */
! 384: u_int ic_size; /* size of I-cache (in bytes) */
! 385: struct cache_cf ic_conf;/* cache configuration (see above) */
! 386: u_int ic_base; /* start addr of I-cache (for FICE flush) */
! 387: u_int ic_stride; /* addr incr per i_count iteration (flush) */
! 388: u_int ic_count; /* number of i_loop iterations (flush) */
! 389: u_int ic_loop; /* number of FICE's per addr stride (flush) */
! 390: /* Data cache */
! 391: u_int dc_size; /* size of D-cache (in bytes) */
! 392: struct cache_cf dc_conf;/* cache configuration (see above) */
! 393: u_int dc_base; /* start addr of D-cache (for FDCE flush) */
! 394: u_int dc_stride; /* addr incr per d_count iteration (flush) */
! 395: u_int dc_count; /* number of d_loop iterations (flush) */
! 396: u_int dc_loop; /* number of FDCE's per addr stride (flush) */
! 397: /* Instruction TLB */
! 398: u_int it_size; /* number of entries in I-TLB */
! 399: struct tlb_cf it_conf; /* I-TLB configuration (see above) */
! 400: u_int it_sp_base; /* start space of I-TLB (for PITLBE flush) */
! 401: u_int it_sp_stride; /* space incr per sp_count iteration (flush) */
! 402: u_int it_sp_count; /* number of off_count iterations (flush) */
! 403: u_int it_off_base; /* start offset of I-TLB (for PITLBE flush) */
! 404: u_int it_off_stride; /* offset incr per off_count iteration (flush)*/
! 405: u_int it_off_count; /* number of it_loop iterations/space (flush) */
! 406: u_int it_loop; /* number of PITLBE's per off_stride (flush) */
! 407: /* Data TLB */
! 408: u_int dt_size; /* number of entries in D-TLB */
! 409: struct tlb_cf dt_conf; /* D-TLB configuration (see above) */
! 410: u_int dt_sp_base; /* start space of D-TLB (for PDTLBE flush) */
! 411: u_int dt_sp_stride; /* space incr per sp_count iteration (flush) */
! 412: u_int dt_sp_count; /* number of off_count iterations (flush) */
! 413: u_int dt_off_base; /* start offset of D-TLB (for PDTLBE flush) */
! 414: u_int dt_off_stride; /* offset incr per off_count iteration (flush)*/
! 415: u_int dt_off_count; /* number of dt_loop iterations/space (flush) */
! 416: u_int dt_loop; /* number of PDTLBE's per off_stride (flush) */
! 417: u_int filler[2];
! 418: };
! 419:
! 420: struct pdc_spidb { /* PDC_CACHE, PDC_CACHE_GETSPIDB */
! 421: u_int spidR1 : 4;
! 422: u_int spidbits : 12;
! 423: u_int spidR2 : 16;
! 424: u_int filler[31];
! 425: };
! 426:
! 427: struct pdc_cst {
! 428: u_int cstR1 : 16;
! 429: u_int cst : 3;
! 430: u_int cstR2 : 13;
! 431: };
! 432:
! 433: struct pdc_coherence { /* PDC_CACHE, PDC_CACHE_SETCS */
! 434: struct pdc_cst ia;
! 435: #define ia_cst ia.cst
! 436: struct pdc_cst da;
! 437: #define da_cst da.cst
! 438: struct pdc_cst ita;
! 439: #define ita_cst ita.cst
! 440: struct pdc_cst dta;
! 441: #define dta_cst dta.cst
! 442: u_int filler[28];
! 443: };
! 444:
! 445: struct pdc_hpa { /* PDC_HPA */
! 446: u_int hpa; /* HPA of processor */
! 447: int filler1;
! 448: u_int filler2[30];
! 449: };
! 450:
! 451: struct pdc_coproc { /* PDC_COPROC */
! 452: u_int ccr_enable; /* same format as CCR (CR 10) */
! 453: u_int ccr_present; /* which co-proc's are present (bitset) */
! 454: u_int pad[15];
! 455: u_int fpu_revision;
! 456: u_int fpu_model;
! 457: u_int filler2[13];
! 458: };
! 459:
! 460: struct pdc_tod { /* PDC_TOD, PDC_TOD_READ */
! 461: u_int sec; /* elapsed time since 00:00:00 GMT, 1/1/70 */
! 462: u_int usec; /* accurate to microseconds */
! 463: u_int filler2[30];
! 464: };
! 465:
! 466: struct pdc_itimer { /* PDC_TOD_ITIMER */
! 467: u_int calib0; /* double giving itmr freq */
! 468: u_int calib1;
! 469: u_int tod_acc; /* TOD accuracy in 1e-9 part */
! 470: u_int cr_acc; /* itmr accuracy in 1e-9 parts */
! 471: u_int filler[28];
! 472: };
! 473:
! 474: struct pdc_nvm { /* PDC_NVM */
! 475: u_int hv[9]; /* 0x00: HV dependent */
! 476: struct device_path bootpath; /* 0x24: boot path */
! 477: u_int isl_ver; /* 0x44: ISL revision */
! 478: u_int timestamp; /* 0x48: timestamp */
! 479: u_int lif_ue[12]; /* 0x4c: LIF utility entries */
! 480: u_int eptr; /* 0x7c: entry pointer */
! 481: u_int os_panic[32]; /* 0x80: OS panic info */
! 482: };
! 483:
! 484: struct pdc_instr { /* PDC_INSTR */
! 485: u_int instr; /* instruction that invokes PDC mchk entry pt */
! 486: int filler1;
! 487: u_int filler2[30];
! 488: };
! 489:
! 490: struct pdc_iodc_read { /* PDC_IODC, PDC_IODC_READ */
! 491: int size; /* number of bytes in selected entry point */
! 492: int filler1;
! 493: u_int filler2[30];
! 494: };
! 495:
! 496: struct pdc_iodc_minit { /* PDC_IODC, PDC_IODC_NINIT or PDC_IODC_DINIT */
! 497: u_int stat; /* HPA.io_status style error returns */
! 498: u_int max_spa; /* size of SPA (in bytes) > max_mem+map_mem */
! 499: u_int max_mem; /* size of "implemented" memory (in bytes) */
! 500: u_int map_mem; /* size of "mappable-only" memory (in bytes) */
! 501: u_int filler[28];
! 502: };
! 503:
! 504: struct btlb_info { /* for "struct pdc_btlb" (PDC_BTLB) */
! 505: u_int resv0: 8, /* (reserved) */
! 506: num_i: 8, /* Number of instruction slots */
! 507: num_d: 8, /* Number of data slots */
! 508: num_c: 8; /* Number of combined slots */
! 509: };
! 510:
! 511: struct pdc_btlb { /* PDC_BLOCK_TLB */
! 512: u_int min_size; /* Min size in pages */
! 513: u_int max_size; /* Max size in pages */
! 514: struct btlb_info finfo; /* Fixed range info */
! 515: struct btlb_info vinfo; /* Variable range info */
! 516: u_int filler[28];
! 517: };
! 518:
! 519: struct pdc_hwtlb { /* PDC_TLB */
! 520: u_int min_size; /* What do these mean? */
! 521: u_int max_size;
! 522: u_int filler[30];
! 523: };
! 524:
! 525: struct pdc_power_info { /* PDC_SOFT_POWER_INFO */
! 526: u_int addr; /* power register address */
! 527: u_int filler[30];
! 528: };
! 529:
! 530: struct pdc_sysmap_find { /* PDC_SYSMAP_FIND */
! 531: u_int hpa;
! 532: u_int size; /* pages */
! 533: u_int naddrs;
! 534: u_int filler[29];
! 535: };
! 536:
! 537: struct pdc_sysmap_addrs { /* PDC_SYSMAP_ADDR */
! 538: u_int hpa;
! 539: u_int size; /* pages */
! 540: u_int filler[30];
! 541: };
! 542:
! 543: struct pdc_sysmap_hpa { /* PDC_SYSMAP_HPA */
! 544: u_int hpa;
! 545: u_int size;
! 546: u_int naddrs;
! 547: u_int mod;
! 548: u_int filler[28];
! 549: };
! 550:
! 551: struct pdc_pat_cell_id { /* PDC_PAT_CELL_GETID */
! 552: u_long id; /* cell id */
! 553: u_long loc; /* cell location */
! 554: u_long filler[14];
! 555: };
! 556:
! 557: struct pdc_pat_cell_module { /* PDC_PAT_CELL_MODULE */
! 558: u_long chpa; /* config space HPA */
! 559: u_long info; /* module info */
! 560: #define PDC_PAT_CELL_MODTYPE(t) (((t) >> 56) & 0xff)
! 561: #define PDC_PAT_CELL_MODDVI(t) (((t) >> 48) & 0xff)
! 562: #define PDC_PAT_CELL_MODIOC(t) (((t) >> 40) & 0xff)
! 563: #define PDC_PAT_CELL_MODSIZE(t) (((t) & 0xffffff) << PAGE_SHIFT)
! 564: u_long loc; /* module location */
! 565: struct device_path dp; /* module path */
! 566: u_long pad[508]; /* cell module gedoens */
! 567: };
! 568:
! 569: struct pdc_pat_io_num { /* PDC_PAT_IO */
! 570: u_int num;
! 571: u_int filler[31];
! 572: };
! 573:
! 574: struct pdc_pat_pci_rt { /* PDC_PAT_IO_GET_PCI_RT */
! 575: u_int8_t type; /* 0x8b */
! 576: u_int8_t len;
! 577: u_int8_t itype; /* 0 -- vectored int */
! 578: u_int8_t trigger; /* polarity/level */
! 579: u_int8_t pin; /* PCI pin number */
! 580: u_int8_t bus;
! 581: u_int8_t seg; /* reserved */
! 582: u_int8_t line;
! 583: u_int64_t addr; /* io sapic address */
! 584: };
! 585:
! 586: struct pdc_memmap { /* PDC_MEMMAP */
! 587: u_int hpa; /* HPA for module */
! 588: u_int morepages; /* additional IO pages */
! 589: u_int filler[30];
! 590: };
! 591:
! 592: struct pdc_lan_station_id { /* PDC_LAN_STATION_ID */
! 593: u_int8_t addr[6];
! 594: u_int8_t filler1[2];
! 595: u_int filler2[30];
! 596: };
! 597:
! 598: /*
! 599: * The PDC_CHASSIS is a strange bird. The format for updating the display
! 600: * is as follows:
! 601: *
! 602: * 0 11 12 14 15 16 19 20 23 24 27 28 31
! 603: * +-------+----------+-------+--------+--------+--------+--------+
! 604: * | R | OS State | Blank | Hex1 | Hex2 | Hex3 | Hex4 |
! 605: * +-------+----------+-------+--------+--------+--------+--------+
! 606: *
! 607: * Unfortunately, someone forgot to tell the hardware designers that
! 608: * there was supposed to be a hex display somewhere. The result is,
! 609: * you can only toggle 5 LED's and the fault light.
! 610: *
! 611: * Interesting values for Hex1-Hex4 and the resulting LED displays:
! 612: *
! 613: * FnFF CnFF:
! 614: * 0 - - - - - Counts in binary from 0x0 - 0xF
! 615: * 2 o - - - - for corresponding values of `n'.
! 616: * 4 o o - - -
! 617: * 6 o o o - -
! 618: * 8 o o o o -
! 619: * A o o o o o
! 620: *
! 621: * If the "Blank" bit is set, the display should be made blank.
! 622: * The values for "OS State" are defined below.
! 623: */
! 624:
! 625: #define PDC_CHASSIS_BAR 0xF0FF /* create a bar graph with LEDs */
! 626: #define PDC_CHASSIS_CNT 0xC0FF /* count with LEDs */
! 627:
! 628: #define PDC_OSTAT(os) (((os) & 0x7) << 17)
! 629: #define PDC_OSTAT_OFF 0x0 /* all off */
! 630: #define PDC_OSTAT_FAULT 0x1 /* the red LED of death */
! 631: #define PDC_OSTAT_TEST 0x2 /* self test */
! 632: #define PDC_OSTAT_BOOT 0x3 /* boot program running */
! 633: #define PDC_OSTAT_SHUT 0x4 /* shutdown in progress */
! 634: #define PDC_OSTAT_WARN 0x5 /* battery dying, etc */
! 635: #define PDC_OSTAT_RUN 0x6 /* OS running */
! 636: #define PDC_OSTAT_ON 0x7 /* all on */
! 637:
! 638: struct pdc_chassis_info {
! 639: u_int size;
! 640: u_int max_size;
! 641: u_int filler[30];
! 642: };
! 643:
! 644: struct pdc_chassis_lcd {
! 645: u_int model : 16,
! 646: width : 16;
! 647: u_int cmd_addr;
! 648: u_int data_addr;
! 649: u_int delay;
! 650: u_int8_t line[2];
! 651: u_int8_t enabled;
! 652: u_int8_t heartbeat[3];
! 653: u_int8_t disk[3];
! 654: u_int filler[25];
! 655: };
! 656:
! 657: /* dp_flags */
! 658: #define PZF_AUTOBOOT 0x80 /* These two are PDC flags for how to locate */
! 659: #define PZF_AUTOSEARCH 0x40 /* the "boot device" */
! 660: #define PZF_TIMER 0x0f /* power of 2 # secs "boot timer" (0 == dflt) */
! 661: #define PZF_BITS "\020\010autoboot\07autosearch"
! 662:
! 663: /* macros to decode serial parameters out of dp_layers */
! 664: #define PZL_BITS(l) (((l) & 0x03) + 5)
! 665: #define PZL_PARITY(l) (((l) & 0x18) >> 3)
! 666: #define PZL_SPEED(l) (((l) & 0x3c0) >> 6)
! 667: #define PZL_ENCODE(bits, parity, speed) \
! 668: (((bits) - 5) & 0x03) | (((parity) & 0x3) << 3) | \
! 669: (((speed) & 0x0f) << 6)
! 670:
! 671: /*
! 672: * A processors Stable Storage is accessed through the PDC. There are
! 673: * at least 96 bytes of stable storage (the device path information may
! 674: * or may not exist). However, as far as I know, processors provide at
! 675: * least 192 bytes of stable storage.
! 676: */
! 677: struct stable_storage {
! 678: struct device_path ss_pri_boot; /* (see above) */
! 679: char ss_filenames[32];
! 680: u_short ss_os_version; /* 0 == none, 1 == HP-UX, 2 == MPE-XL */
! 681: char ss_os[22]; /* OS-dependant information */
! 682: char ss_pdc[7]; /* reserved */
! 683: char ss_fast_size; /* how much memory to test. 0xf == all, or */
! 684: /* else it's (256KB << ss_fast_size) */
! 685: struct device_path ss_console;
! 686: struct device_path ss_alt_boot;
! 687: struct device_path ss_keyboard;
! 688: };
! 689:
! 690: /*
! 691: * Recoverable error indications provided to boot code by the PDC.
! 692: * Any non-zero value indicates error.
! 693: */
! 694: struct boot_err {
! 695: u_int be_resv : 10, /* (reserved) */
! 696: be_fixed : 6, /* module that produced error */
! 697: be_chas : 16; /* error code (interpret as 4 hex digits) */
! 698: };
! 699:
! 700: #define HPBE_HBOOT_CORRECTABLE 0 /* hard-boot corrctable error */
! 701: #define HPBE_HBOOT_UNCORRECTBL 1 /* hard-boot uncorrectable error */
! 702: #define HPBE_SBOOT_CORRECTABLE 2 /* soft-boot correctable error */
! 703: #define HPBE_SBOOT_UNCORRECTBL 3 /* soft-boot uncorrectable error */
! 704: #define HPBE_ETEST_MODUNUSABLE 4 /* ENTRY_TEST err: module's unusable */
! 705: #define HPBE_ETEST_MODDEGRADED 5 /* ENTRY_TEST err: module in degraded mode */
! 706:
! 707:
! 708: /*
! 709: * The PDC uses the following structure to completely define an I/O
! 710: * module and the interface to its IODC.
! 711: */
! 712: typedef
! 713: struct pz_device {
! 714: struct device_path pz_dp;
! 715: #define pz_flags pz_dp.dp_flags
! 716: #define pz_bc pz_dp.dp_bc
! 717: #define pz_mod pz_dp.dp_mod
! 718: #define pz_layers pz_dp.dp_layers
! 719: u_int pz_hpa; /* HPA base address of device */
! 720: u_int pz_spa; /* SPA base address (zero if no SPA exists) */
! 721: u_int pz_iodc_io; /* entry point of device's driver routines */
! 722: short pz_resv; /* (reserved) */
! 723: u_short pz_class; /* (see below) */
! 724: } pz_device_t;
! 725:
! 726: /* pz_class */
! 727: #define PCL_NULL 0 /* illegal */
! 728: #define PCL_RANDOM 1 /* random access (disk) */
! 729: #define PCL_SEQU 2 /* sequential access (tape) */
! 730: #define PCL_DUPLEX 7 /* full-duplex point-to-point (RS-232, Net) */
! 731: #define PCL_KEYBD 8 /* half-duplex input (HIL Keyboard) */
! 732: #define PCL_DISPL 9 /* half-duplex ouptput (display) */
! 733: #define PCL_FC 10 /* fibre channel access media */
! 734: #define PCL_CLASS_MASK 0xf /* XXX class mask */
! 735: #define PCL_NET_MASK 0x1000 /* mask for bootp/tftp device */
! 736:
! 737: /*
! 738: * The following structure defines what a particular IODC returns when
! 739: * given the IODC_DATA argument.
! 740: */
! 741: struct iodc_data {
! 742: u_int iodc_model: 8, /* hardware model number */
! 743: iodc_revision:8, /* software revision */
! 744: iodc_spa_io: 1, /* 0:memory, 1:device */
! 745: iodc_spa_pack:1, /* 1:packed multiplexor */
! 746: iodc_spa_enb:1, /* 1:has an spa */
! 747: iodc_spa_shift:5, /* power of two # bytes in SPA space */
! 748: iodc_more: 1, /* iodc_data is: 0:8-byte, 1:16-byte */
! 749: iodc_word: 1, /* iodc_data is: 0:byte, 1:word */
! 750: iodc_pf: 1, /* 1:supports powerfail */
! 751: iodc_type: 5; /* see below */
! 752: u_int iodc_sv_rev: 4, /* software version revision number */
! 753: iodc_sv_model:20, /* software interface model # */
! 754: iodc_sv_opt: 8; /* type-specific options */
! 755: u_char iodc_rev; /* revision number of IODC code */
! 756: u_char iodc_dep; /* module-dependent information */
! 757: u_char iodc_rsv[2]; /* reserved */
! 758: u_short iodc_cksum; /* 16-bit checksum of whole IODC */
! 759: u_short iodc_length; /* number of entry points in IODC */
! 760: /* IODC entry points follow... */
! 761: };
! 762:
! 763: extern pdcio_t pdc;
! 764:
! 765: #ifdef _KERNEL
! 766: struct consdev;
! 767:
! 768: extern int kernelmapped;
! 769:
! 770: void pdc_init(void);
! 771: int pdc_call(iodcio_t, int, ...);
! 772:
! 773: void pdccnprobe(struct consdev *);
! 774: void pdccninit(struct consdev *);
! 775: int pdccngetc(dev_t);
! 776: void pdccnputc(dev_t, int);
! 777: void pdccnpollc(dev_t, int);
! 778: #endif
! 779:
! 780: #endif /* !(_LOCORE) */
! 781:
! 782: #endif /* _MACHINE_PDC_H_ */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to pdc.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / hppa / include