Annotation of sys/arch/hppa/include/intr.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: intr.h,v 1.23 2007/05/16 19:37:06 thib Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 2002-2004 Michael Shalayeff
! 5: * All rights reserved.
! 6: *
! 7: * Redistribution and use in source and binary forms, with or without
! 8: * modification, are permitted provided that the following conditions
! 9: * are met:
! 10: * 1. Redistributions of source code must retain the above copyright
! 11: * notice, this list of conditions and the following disclaimer.
! 12: * 2. Redistributions in binary form must reproduce the above copyright
! 13: * notice, this list of conditions and the following disclaimer in the
! 14: * documentation and/or other materials provided with the distribution.
! 15: *
! 16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 19: * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
! 20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 22: * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
! 24: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
! 25: * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
! 26: * THE POSSIBILITY OF SUCH DAMAGE.
! 27: */
! 28:
! 29: #ifndef _MACHINE_INTR_H_
! 30: #define _MACHINE_INTR_H_
! 31:
! 32: #include <machine/psl.h>
! 33:
! 34: #define CPU_NINTS 32
! 35: #define NIPL 16
! 36:
! 37: #define IPL_NONE 0
! 38: #define IPL_SOFTCLOCK 1
! 39: #define IPL_SOFTNET 2
! 40: #define IPL_BIO 3
! 41: #define IPL_NET 4
! 42: #define IPL_SOFTTTY 5
! 43: #define IPL_TTY 6
! 44: #define IPL_VM 7
! 45: #define IPL_AUDIO 8
! 46: #define IPL_CLOCK 9
! 47: #define IPL_STATCLOCK 10
! 48: #define IPL_HIGH 10
! 49: #define IPL_NESTED 11 /* pseudo-level for sub-tables */
! 50:
! 51: #define IST_NONE 0
! 52: #define IST_PULSE 1
! 53: #define IST_EDGE 2
! 54: #define IST_LEVEL 3
! 55:
! 56: #if !defined(_LOCORE) && defined(_KERNEL)
! 57:
! 58: #include <machine/atomic.h>
! 59:
! 60: extern volatile int cpl;
! 61: extern volatile u_long ipending, imask[NIPL];
! 62: extern int astpending;
! 63:
! 64: #ifdef DIAGNOSTIC
! 65: void splassert_fail(int, int, const char *);
! 66: extern int splassert_ctl;
! 67: void splassert_check(int, const char *);
! 68: #define splassert(__wantipl) do { \
! 69: if (splassert_ctl > 0) { \
! 70: splassert_check(__wantipl, __func__); \
! 71: } \
! 72: } while (0)
! 73: #else
! 74: #define splassert(__wantipl) do { /* nada */ } while (0)
! 75: #endif /* DIAGNOSTIC */
! 76:
! 77: void cpu_intr_init(void);
! 78: void cpu_intr(void *);
! 79:
! 80: static __inline int
! 81: spllower(int ncpl)
! 82: {
! 83: register int ocpl asm("r28") = ncpl;
! 84: __asm __volatile("copy %0, %%arg0\n\tbreak %1, %2"
! 85: : "+r" (ocpl) : "i" (HPPA_BREAK_KERNEL), "i" (HPPA_BREAK_SPLLOWER)
! 86: : "r26", "memory");
! 87: return (ocpl);
! 88: }
! 89:
! 90: static __inline int
! 91: splraise(int ncpl)
! 92: {
! 93: int ocpl = cpl;
! 94:
! 95: if (ocpl < ncpl)
! 96: cpl = ncpl;
! 97: __asm __volatile ("sync" : "+r" (cpl));
! 98:
! 99: return (ocpl);
! 100: }
! 101:
! 102: static __inline void
! 103: splx(int ncpl)
! 104: {
! 105: (void)spllower(ncpl);
! 106: }
! 107:
! 108: #define splsoftclock() splraise(IPL_SOFTCLOCK)
! 109: #define splsoftnet() splraise(IPL_SOFTNET)
! 110: #define splbio() splraise(IPL_BIO)
! 111: #define splnet() splraise(IPL_NET)
! 112: #define splsofttty() splraise(IPL_SOFTTTY)
! 113: #define spltty() splraise(IPL_TTY)
! 114: #define splvm() splraise(IPL_VM)
! 115: #define splaudio() splraise(IPL_AUDIO)
! 116: #define splclock() splraise(IPL_CLOCK)
! 117: #define splsched() splraise(IPL_SCHED)
! 118: #define splstatclock() splraise(IPL_STATCLOCK)
! 119: #define splhigh() splraise(IPL_HIGH)
! 120: #define spl0() spllower(IPL_NONE)
! 121:
! 122: #define softintr(mask) atomic_setbits_long(&ipending, mask)
! 123:
! 124: #define SOFTINT_MASK ((1 << (IPL_SOFTCLOCK - 1)) | \
! 125: (1 << (IPL_SOFTNET - 1)) | (1 << (IPL_SOFTTTY - 1)))
! 126:
! 127: #define setsoftast() (astpending = 1)
! 128: #define setsoftclock() softintr(1 << (IPL_SOFTCLOCK - 1))
! 129: #define setsoftnet() softintr(1 << (IPL_SOFTNET - 1))
! 130: #define setsofttty() softintr(1 << (IPL_SOFTTTY - 1))
! 131:
! 132: #endif /* !_LOCORE && _KERNEL */
! 133: #endif /* _MACHINE_INTR_H_ */
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