Annotation of sys/arch/hppa/dev/viper.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: viper.h,v 1.6 2007/04/10 17:47:54 miod Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 1991,1994 The University of Utah and
! 5: * the Computer Systems Laboratory (CSL). All rights reserved.
! 6: *
! 7: * Permission to use, copy, modify and distribute this software is hereby
! 8: * granted provided that (1) source code retains these copyright, permission,
! 9: * and disclaimer notices, and (2) redistributions including binaries
! 10: * reproduce the notices in supporting documentation, and (3) all advertising
! 11: * materials mentioning features or use of this software display the following
! 12: * acknowledgement: ``This product includes software developed by the
! 13: * Computer Systems Laboratory at the University of Utah.''
! 14: *
! 15: * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
! 16: * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
! 17: * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
! 18: *
! 19: * CSL requests users of this software to return to csl-dist@cs.utah.edu any
! 20: * improvements that they make and grant CSL redistribution rights.
! 21: *
! 22: * Utah $Hdr: viper.h 1.8 94/12/14$
! 23: */
! 24:
! 25: /*
! 26: * Viper control register.
! 27: *
! 28: * With respect to arbitration preference (*_prf), only one of these may be
! 29: * set at any one time. "preference" means that a particular device will
! 30: * be granted the bus on every other arbitration cycle; these bits default
! 31: * to unset (0). Similarly, a device may be denied the bus (*_den); these
! 32: * bits default to *set* (1).
! 33: *
! 34: * The macros V_CTRL_ANYPRF or V_CTRL_ANYDEN should be used to determine
! 35: * if any preference or deny bits are set.
! 36: */
! 37:
! 38: #define VI_CTRL_EISA_DEN 0x00000001 /* EISA denied bus grants */
! 39: #define VI_CTRL_EISA_PRF 0x00000002 /* EISA bus has arbitration preference */
! 40: #define VI_CTRL_CORE_DEN 0x00000004 /* CORE denied bus grants */
! 41: #define VI_CTRL_CORE_PRF 0x00000008 /* CORE bus has arbitration preference */
! 42: #define VI_CTRL_SGC0_DEN 0x00000010 /* SGC0 denied bus grants */
! 43: #define VI_CTRL_SGC0_PRF 0x00000020 /* SGC0 has arbitration preference */
! 44: #define VI_CTRL_SGC1_DEN 0x00000040 /* SGC1 denied bus grants */
! 45: #define VI_CTRL_SGC1_PRF 0x00000080 /* SGC1 has arbitration preference */
! 46: #define VI_CTRL_CPU_PRF 0x00000200 /* CPU has arbitration preference */
! 47: #define VI_CTRL_LPMC_EN 0x00010000 /* enable Low Priority Machine Checks */
! 48: #define VI_CTRL_IPREF_EN 0x00020000 /* enable instruction prefetching */
! 49: #define VI_CTRL_VSC_TOUT 0xfff80000 /* VSC clocks to wait before buserr tmo */
! 50:
! 51: #define VI_CTRL_ANYPRF 0x02AA
! 52: #define VI_CTRL_ANYDEN 0x0055
! 53: #define VI_CTRL PAGE0->pz_Pdep.pd_Viper.v_Ctrlcpy
! 54: #define VI_CTRL_BITS "\020\001eisa_den\002eisa_prf\003core_den\004core_prf" \
! 55: "\005sgc1_den\006sgc1_prf\007sgc0_den\010sgc0_prf" \
! 56: "\012cpu_prf\021lpmc_en\022ipref_en"
! 57:
! 58: #define VI_STAT_BITS "\020\001grf_buserr\002cpu_buserr\003ven_tmo" \
! 59: "\004ven_buserr\005toc\006hardecc\007softecc\010cmdrst"
! 60: struct vi_stat { /* (RO) */
! 61: u_int hw_rev :24, /* Viper hardware revision (24 bits!) */
! 62: cmdreset: 1, /* set if last chip reset caused by CMD_RESET */
! 63: softecc : 1, /* correctable memory error (lpmc_en set) */
! 64: hardecc : 1, /* uncorrectable memory error (HPMC) */
! 65: toc : 1, /* Transfer Of Control signaled */
! 66: vn_ader : 1, /* Venom address error (lpmc_en set) */
! 67: vn_vscto: 1, /* Venom VSC timeout (lpmc_en set) */
! 68: cpu_ader: 1, /* CPU address error or timeout (HPMC) */
! 69: grf_ader: 1; /* Graphics address error */
! 70: };
! 71:
! 72:
! 73: /*
! 74: * Viper TRS. The structures have been defined above; the remaining
! 75: * fields are described here.
! 76: *
! 77: * vi_intrwd (WO)
! 78: * If a high to low transition of the interrupt line occurs,
! 79: * Viper will send this to the CPU to be or'd into its EIR.
! 80: * In general, this is an ASP interrupt request.
! 81: *
! 82: * vi_mem_ctrl (WO)
! 83: * Set various DRAM attributes (row, cols, refresh, etc).
! 84: *
! 85: * vi_mem_wrchk (WO), vi_mem_rdchk (RO)
! 86: * read/write data to be for copyin/memtest.
! 87: *
! 88: * vi_mem_limit (WO)
! 89: * Set an upper limit for non-IO memory accesses; this must
! 90: * be less than the actual memory size, low 22 bits ignored.
! 91: *
! 92: * vi_merr_w0, vi_merr_w1, vi_merr_ckbyte, vi_merr_addr (RO)
! 93: * If memory error detection enabled and soft/hard ECC error,
! 94: * raw double word is stored here (w0: most significant word).
! 95: * The raw checkbyte data is stored in "vi_merr_ckbyte".
! 96: * The address of last logged error is in "vi_merr_addr".
! 97: *
! 98: */
! 99: struct vi_trs {
! 100: u_int vi_control; /* PAGE0->pz_Pdep.pd_Viper.v_Ctrlcpy */
! 101: struct vi_stat vi_status;
! 102: u_int vi_intrwd;
! 103: u_int vi_resv1[13];
! 104: u_int vi_mem_ctrl;
! 105: u_int vi_mem_wrchk;
! 106: u_int vi_mem_limit;
! 107: u_int vi_resv2[1];
! 108: u_int vi_merr_w1;
! 109: u_int vi_merr_w2;
! 110: u_int vi_merr_ckbyte;
! 111: u_int vi_mem_rdchk;
! 112: u_int vi_merr_addr;
! 113: u_int vi_resv3[135];
! 114: };
! 115:
! 116:
! 117: /*
! 118: ** Viper also creates HPA registers for the graphics accelerator (Venom).
! 119: ** Venom has two sets of resisters; the User HPA contains registers that
! 120: ** users are allowed to access, while the Supervisor HPA is only accessible
! 121: ** by code running at the most priviliged level. Both sets of registers
! 122: ** are defined below.
! 123: */
! 124:
! 125: #define VENOM_USER ((struct vn_user *)0xFFFBC000)
! 126: #define VENOM_SUPR ((struct vn_supr *)0xFFFBD000)
! 127:
! 128: /*
! 129: * Define bits in the Venom "User Control" register.
! 130: */
! 131: struct vnu_ctl {
! 132: u_int sdt_msk :16, /* screen door transparancy mask */
! 133: : 6,
! 134: d_z_intp: 1, /* disable Z Interpolation when set */
! 135: d_c_intp: 1, /* disable Color Interpolation when set */
! 136: d_ad_inc: 1, /* disable I/O Addr Incrementing when set */
! 137: : 1,
! 138: z_fast : 1, /* enable Fast Z Interpolation when set */
! 139: c_pseudo: 1, /* enable Pseudo Color when set (disable RG) */
! 140: z_prec24: 1, /* enable 24-bit Z integer precision (o/w 16) */
! 141: cmp_intp: 3; /* enable cond: Z intp owrites old Z (<,>,=) */
! 142: };
! 143:
! 144: /*
! 145: * When vnu_ctl's "z_prec24" is set, 24-bit Z integer precision is enabled
! 146: * (otherwise 16-bit integer precision is used). When enabled, the format
! 147: * of various User Control registers is changed; `vnu_prec' (defined below)
! 148: * should make this format more clear.
! 149: */
! 150: union vnu_prec { /* 16 or 24 bit precision */
! 151: struct {
! 152: u_int zero1; /* must be zero */
! 153: u_int intg :16, /* integer part (16 bits) */
! 154: frac :12, /* fractional part (12 bits) */
! 155: zero2 : 4; /* must be zero */
! 156: } prec16;
! 157: struct {
! 158: u_int frac_lo : 4, /* fractional part (lower 4 bits) */
! 159: zero1 :28; /* must be zero */
! 160: u_int intg :24, /* integer part (24 bits) */
! 161: frac_hi : 8; /* fractional part (upper 8 bits) */
! 162: } prec24;
! 163: };
! 164: #define vnu_p16i prec16.intg
! 165: #define vnu_p16f prec16.frac
! 166: #define vnu_p24i prec24.intg
! 167: #define vnu_p24f ((prec24.frac_hi << 4) | prec24.frac_lo)
! 168: #define vnu_p24fh prec24.frac_hi
! 169: #define vnu_p24fl prec24.frac_lo
! 170:
! 171: /*
! 172: * Venom User HPA registers.
! 173: */
! 174: struct vn_user {
! 175: u_int vnu_resv1[32];
! 176: struct vnu_ctl vnu_uctl; /* user control */
! 177: u_int vnu_spancnt; /* span count (13 bits, signed) */
! 178: u_int vnu_graddr; /* graphics address (24 bits: 6-29) */
! 179: u_int vnu_resv2;
! 180: union vnu_prec vnu_zslope; /* Z Slope */
! 181: union vnu_prec vnu_z; /* Z */
! 182: u_int vnu_resv3[8];
! 183: u_int vnu_bslope; /* Blue Slope (12-19:int, 20-31:fra) */
! 184: u_int vnu_bcolor; /* Blue Color (12-19:int, 20-31:fra) */
! 185: u_int vnu_resv4[2];
! 186: u_int vnu_rslope; /* Red Slope (12-19:int, 20-31:fra) */
! 187: u_int vnu_rcolor; /* Red Color (12-19:int, 20-31:fra) */
! 188: u_int vnu_resv5[2];
! 189: u_int vnu_gslope; /* Green Slope (12-19:int, 20-31:fra) */
! 190: u_int vnu_gcolor; /* Green Color (12-19:int, 20-31:fra) */
! 191: };
! 192:
! 193:
! 194: /*
! 195: * Define bits in Venom "Supervisor Control" register.
! 196: */
! 197: struct vns_ctl {
! 198: u_int : 4,
! 199: ioaddr : 2, /* graphics addr (bits 4 & 5 of `vnu_graddr') */
! 200: d_venom : 1, /* disable Venom operation processing */
! 201: :25;
! 202: };
! 203:
! 204: /*
! 205: * Venom Supervisor HPA registers.
! 206: */
! 207: struct vn_supr {
! 208: u_int vns_resv1[32];
! 209: struct vns_ctl vns_sctl; /* supervisor control */
! 210: u_int vns_zaddr; /* Z Buffer Address (RO) */
! 211: };
! 212:
! 213: void viper_setintrwnd(u_int32_t mask);
! 214: void viper_eisa_en(void);
! 215:
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