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Annotation of sys/arch/hp300/hp300/clockreg.h, Revision 1.1

1.1     ! nbrk        1: /*     $OpenBSD: clockreg.h,v 1.5 2005/01/14 22:39:27 miod Exp $       */
        !             2: /*     $NetBSD: clockreg.h,v 1.5 1994/10/26 07:25:26 cgd Exp $ */
        !             3:
        !             4: /*
        !             5:  * Copyright (c) 1988 University of Utah.
        !             6:  * Copyright (c) 1982, 1990, 1993
        !             7:  *     The Regents of the University of California.  All rights reserved.
        !             8:  *
        !             9:  * This code is derived from software contributed to Berkeley by
        !            10:  * the Systems Programming Group of the University of Utah Computer
        !            11:  * Science Department.
        !            12:  *
        !            13:  * Redistribution and use in source and binary forms, with or without
        !            14:  * modification, are permitted provided that the following conditions
        !            15:  * are met:
        !            16:  * 1. Redistributions of source code must retain the above copyright
        !            17:  *    notice, this list of conditions and the following disclaimer.
        !            18:  * 2. Redistributions in binary form must reproduce the above copyright
        !            19:  *    notice, this list of conditions and the following disclaimer in the
        !            20:  *    documentation and/or other materials provided with the distribution.
        !            21:  * 3. Neither the name of the University nor the names of its contributors
        !            22:  *    may be used to endorse or promote products derived from this software
        !            23:  *    without specific prior written permission.
        !            24:  *
        !            25:  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
        !            26:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
        !            27:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
        !            28:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
        !            29:  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
        !            30:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
        !            31:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
        !            32:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
        !            33:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
        !            34:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
        !            35:  * SUCH DAMAGE.
        !            36:  *
        !            37:  * from: Utah $Hdr: clockreg.h 1.14 91/01/18$
        !            38:  *
        !            39:  *     @(#)clockreg.h  8.2 (Berkeley) 1/12/94
        !            40:  */
        !            41:
        !            42: /*
        !            43:  * HP300 "real time clock" (MC6840) registers
        !            44:  */
        !            45:
        !            46: struct clkreg {
        !            47:        u_char  clk_dummy1;
        !            48:        u_char  clk_cr3;
        !            49: #define        clk_cr1 clk_cr3
        !            50:        u_char  clk_dummy2;
        !            51:        u_char  clk_cr2;
        !            52: #define        clk_sr  clk_cr2
        !            53:        u_char  clk_dummy3;
        !            54:        u_char  clk_msb1;
        !            55:        u_char  clk_dummy4;
        !            56:        u_char  clk_lsb1;
        !            57:        u_char  clk_dummy5;
        !            58:        u_char  clk_msb2;
        !            59:        u_char  clk_dummy6;
        !            60:        u_char  clk_lsb2;
        !            61:        u_char  clk_dummy7;
        !            62:        u_char  clk_msb3;
        !            63:        u_char  clk_dummy8;
        !            64:        u_char  clk_lsb3;
        !            65: };
        !            66:
        !            67: /* base/offsets for register access (for locore.s) */
        !            68: #define        CLKBASE         IIOPOFF(0x5F8000)
        !            69: #define        CLKCR1          0x1
        !            70: #define        CLKCR2          0x3
        !            71: #define        CLKCR3          CLKCR1
        !            72: #define        CLKSR           CLKCR2
        !            73: #define        CLKMSB1         0x5
        !            74: #define        CLKMSB2         0x9
        !            75: #define        CLKMSB3         0xD
        !            76:
        !            77: /* output of counter 3 clocks counter 2 */
        !            78:
        !            79: #define        CLK_OENAB       0x80    /* output enable */
        !            80: #define        CLK_IENAB       0x40    /* interrupt enable */
        !            81: #define        CLK_8BIT        0x04    /* 8 bit mode */
        !            82: #define        CLK_RESET       0x01    /* chip reset (CR1 only) */
        !            83: #define        CLK_CR1         0x01    /* select CR1 (CR2 only) */
        !            84: #define        CLK_CR3         0x00    /* select CR3 (CR2 only) */
        !            85: #define CLK_INT1       0x01    /* interrupt flag for timer 1 (SR only) */
        !            86: #define CLK_INT2       0x02    /* interrupt flag for timer 2 (SR only) */
        !            87: #define CLK_INT3       0x04    /* interrupt flag for timer 3 (SR only) */
        !            88: #define        CLK_INTR        0x80    /* composite interrupt flag (SR only) */
        !            89:
        !            90: #define CLK_RESOLUTION 4       /* 4 usec resolution (250KHz) */
        !            91: #define        CLK_INTERVAL    2500    /* 10msec interval at 250KHz */
        !            92: #ifdef NOTDEF
        !            93: #define CLK_INTERVAL   5000    /* 20msec interval at 250KHz */
        !            94: #endif
        !            95:
        !            96: /*
        !            97:  * HP300 battery-backed clock
        !            98:  */
        !            99:
        !           100: #define        BBCADDR         (u_int8_t *)(IIOV(0x420000))
        !           101:
        !           102: struct bbc_tm {
        !           103:        int     tm_sec;
        !           104:        int     tm_min;
        !           105:        int     tm_hour;
        !           106:        int     tm_mday;
        !           107:        int     tm_mon;
        !           108:        int     tm_year;
        !           109: };
        !           110:
        !           111: #define FEBRUARY       2
        !           112: #define        STARTOFTIME     1970
        !           113: #define SECDAY         86400L
        !           114: #define SECYR          (SECDAY * 365)
        !           115:
        !           116: #define BBC_SET_REG    0xe0
        !           117: #define BBC_WRITE_REG  0xc2
        !           118: #define BBC_READ_REG   0xc3
        !           119: #define NUM_BBC_REGS   12
        !           120:
        !           121: #define        leapyear(year)          ((year) % 4 == 0)
        !           122: #define        range_test(n, l, h)     if ((n) < (l) || (n) > (h)) return(0)
        !           123: #define        days_in_year(a)         (leapyear(a) ? 366 : 365)
        !           124: #define        days_in_month(a)        (month_days[(a) - 1])
        !           125: #define        bbc_to_decimal(a,b)     (bbc_registers[a] * 10 + bbc_registers[b])
        !           126: #define        decimal_to_bbc(a,b,n)   { \
        !           127:        bbc_registers[a] = (n) % 10; \
        !           128:        bbc_registers[b] = (n) / 10; \
        !           129: }