Annotation of sys/arch/hp300/dev/mb89352reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: mb89352reg.h,v 1.1 2004/08/03 21:46:56 miod Exp $ */
2: /* $NetBSD: mb89352reg.h,v 1.3 2003/08/07 16:31:02 agc Exp $ */
3: /* NecBSD: mb89352reg.h,v 1.3 1998/03/14 07:04:34 kmatsuda Exp */
4:
5: /*-
6: * Copyright (c) 1990, 1993
7: * The Regents of the University of California. All rights reserved.
8: *
9: * This code is derived from software contributed to The NetBSD Foundation
10: * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda.
11: *
12: * This code is derived from software contributed to Berkeley by
13: * Van Jacobson of Lawrence Berkeley Laboratory.
14: *
15: * Redistribution and use in source and binary forms, with or without
16: * modification, are permitted provided that the following conditions
17: * are met:
18: * 1. Redistributions of source code must retain the above copyright
19: * notice, this list of conditions and the following disclaimer.
20: * 2. Redistributions in binary form must reproduce the above copyright
21: * notice, this list of conditions and the following disclaimer in the
22: * documentation and/or other materials provided with the distribution.
23: * 3. Neither the name of the University nor the names of its contributors
24: * may be used to endorse or promote products derived from this software
25: * without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37: * SUCH DAMAGE.
38: *
39: * @(#)scsireg.h 8.1 (Berkeley) 6/10/93
40: */
41:
42: /*-
43: * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc.
44: * All rights reserved.
45: *
46: * This code is derived from software contributed to The NetBSD Foundation
47: * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda.
48: *
49: * This code is derived from software contributed to Berkeley by
50: * Van Jacobson of Lawrence Berkeley Laboratory.
51: *
52: * Redistribution and use in source and binary forms, with or without
53: * modification, are permitted provided that the following conditions
54: * are met:
55: * 1. Redistributions of source code must retain the above copyright
56: * notice, this list of conditions and the following disclaimer.
57: * 2. Redistributions in binary form must reproduce the above copyright
58: * notice, this list of conditions and the following disclaimer in the
59: * documentation and/or other materials provided with the distribution.
60: * 3. All advertising materials mentioning features or use of this software
61: * must display the following acknowledgement:
62: * This product includes software developed by the University of
63: * California, Berkeley and its contributors.
64: * 4. Neither the name of the University nor the names of its contributors
65: * may be used to endorse or promote products derived from this software
66: * without specific prior written permission.
67: *
68: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
69: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
70: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
71: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
72: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
73: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
74: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
75: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
76: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
77: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
78: * SUCH DAMAGE.
79: *
80: * @(#)scsireg.h 8.1 (Berkeley) 6/10/93
81: */
82: /*
83: * [NetBSD for NEC PC-98 series]
84: * Copyright (c) 1996, 1997, 1998
85: * NetBSD/pc98 porting staff. All rights reserved.
86: * Copyright (c) 1996, 1997, 1998
87: * Kouichi Matsuda. All rights reserved.
88: */
89:
90: /*
91: * FUJITSU MB89352A SCSI Protocol Controller Hardware Description.
92: */
93:
94: /* Definitions, most of them has turned out to be unneccesary, but here they
95: * are anyway.
96: */
97:
98: #define BDID 0x00 /* Bus Device ID (R/W) */
99: #define SCTL 0x01 /* SPC Control register (R/W) */
100: #define SCMD 0x02 /* Command Register (R/W) */
101: #define TMOD 0x03 /* Transmit Mode Register (synch models) */
102: #define INTS 0x04 /* Interrupt sense (R); Interrupt Reset (W) */
103: #define PSNS 0x05 /* Phase Sense (R); SPC Diagnostic Control (W) */
104: #define SSTS 0x06 /* SPC status (R/O) */
105: #define SERR 0x07 /* SPC error status (R/O) */
106: #define PCTL 0x08 /* Phase Control (R/W) */
107: #define MBC 0x09 /* Modified Byte Counter (R/O) */
108: #define DREG 0x0a /* Data Register (R/W) */
109: #define TEMP 0x0b /* Temporary Register (R/W) */
110: #define TCH 0x0c /* Transfer Counter High (R/W) */
111: #define TCM 0x0d /* Transfer Counter Middle (R/W) */
112: #define TCL 0x0e /* Transfer Counter Low (R/W) */
113: #define EXBF 0x0f /* External Buffer (synch models) */
114:
115: /* What all the bits do */
116:
117: /* SCSI_BDID */
118: /* SCSI selection/reselection ID (both target *and* initiator) */
119: #define SELID7 0x80
120: #define SELID6 0x40
121: #define SELID5 0x20
122: #define SELID4 0x10
123: #define SELID3 0x08
124: #define SELID2 0x04
125: #define SELID1 0x02
126: #define SELID0 0x01
127:
128: /* SCSI_SCTL */
129: #define SCTL_DISABLE 0x80
130: #define SCTL_CTRLRST 0x40
131: #define SCTL_DIAG 0x20
132: #define SCTL_ABRT_ENAB 0x10
133: #define SCTL_PARITY_ENAB 0x08
134: #define SCTL_SEL_ENAB 0x04
135: #define SCTL_RESEL_ENAB 0x02
136: #define SCTL_INTR_ENAB 0x01
137:
138: /* SCSI_SCMD */
139: #define SCMD_RST 0x10
140: #define SCMD_ICPT_XFR 0x08
141: #define SCMD_PROG_XFR 0x04
142: #define SCMD_PAD 0x01 /* if initiator */
143: #define SCMD_PERR_STOP 0x01 /* if target */
144: /* command codes */
145: #define SCMD_BUS_REL 0x00
146: #define SCMD_SELECT 0x20
147: #define SCMD_RST_ATN 0x40
148: #define SCMD_SET_ATN 0x60
149: #define SCMD_XFR 0x80
150: #define SCMD_XFR_PAUSE 0xa0
151: #define SCMD_RST_ACK 0xc0
152: #define SCMD_SET_ACK 0xe0
153:
154: /* SCSI_TMOD */
155: #define TMOD_SYNC 0x80
156:
157: /* SCSI_INTS */
158: #define INTS_SEL 0x80
159: #define INTS_RESEL 0x40
160: #define INTS_DISCON 0x20
161: #define INTS_CMD_DONE 0x10
162: #define INTS_SRV_REQ 0x08
163: #define INTS_TIMEOUT 0x04
164: #define INTS_HARD_ERR 0x02
165: #define INTS_RST 0x01
166:
167: /* SCSI_PSNS */
168: #define PSNS_REQ 0x80
169: #define PSNS_ACK 0x40
170: #define PSNS_ATN 0x20
171: #define PSNS_SEL 0x10
172: #define PSNS_BSY 0x08
173:
174: /* PSNS */
175: #define REQI 0x80
176: #define ACKI 0x40
177: #define ATNI 0x20
178: #define SELI 0x10
179: #define BSYI 0x08
180: #define MSGI 0x04
181: #define CDI 0x02
182: #define IOI 0x01
183:
184: /* Important! The 3 most significant bits of this register, in initiator mode,
185: * represents the "expected" SCSI bus phase and can be used to trigger phase
186: * mismatch and phase change interrupts. But more important: If there is a
187: * phase mismatch the chip will not transfer any data! This is actually a nice
188: * feature as it gives us a bit more control over what is happening when we are
189: * bursting data (in) through the FIFOs and the phase suddenly changes from
190: * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the
191: * proper phase to be set in this register instead of dumping the bits into the
192: * FIFOs.
193: */
194: #if 0
195: #define REQO 0x80
196: #define ACKO 0x40
197: #define ATNO 0x20
198: #define SELO 0x10
199: #define BSYO 0x08
200: #endif
201: /* PCTL */
202: #define MSGO 0x04
203: #define CDO 0x02
204: #define IOO 0x01
205:
206: /* Information transfer phases */
207: #define PH_DATAOUT (0)
208: #define PH_DATAIN (IOI)
209: #define PH_CMD (CDI)
210: #define PH_STAT (CDI | IOI)
211: #define PH_MSGOUT (MSGI | CDI)
212: #define PH_MSGIN (MSGI | CDI | IOI)
213:
214: #define PH_MASK (MSGI | CDI | IOI)
215:
216: #define PH_INVALID 0xff
217:
218: /* SCSI_SSTS */
219: #define SSTS_INITIATOR 0x80
220: #define SSTS_TARGET 0x40
221: #define SSTS_BUSY 0x20
222: #define SSTS_XFR 0x10
223: #define SSTS_ACTIVE (SSTS_INITIATOR|SSTS_XFR)
224: #define SSTS_RST 0x08
225: #define SSTS_TCZERO 0x04
226: #define SSTS_DREG_FULL 0x02
227: #define SSTS_DREG_EMPTY 0x01
228:
229: /* SCSI_SERR */
230: #define SERR_SCSI_PAR 0x80
231: #define SERR_SPC_PAR 0x40
232: #define SERR_TC_PAR 0x08
233: #define SERR_PHASE_ERR 0x04
234: #define SERR_SHORT_XFR 0x02
235: #define SERR_OFFSET 0x01
236:
237: /* SCSI_PCTL */
238: #define PCTL_BFINT_ENAB 0x80
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