Annotation of sys/arch/hp300/dev/dcareg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: dcareg.h,v 1.7 2005/12/28 21:13:40 miod Exp $ */
2: /* $NetBSD: dcareg.h,v 1.6 1996/02/24 00:55:02 thorpej Exp $ */
3:
4: /*
5: * Copyright (c) 1982, 1986, 1990, 1993
6: * The Regents of the University of California. All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. Neither the name of the University nor the names of its contributors
17: * may be used to endorse or promote products derived from this software
18: * without specific prior written permission.
19: *
20: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30: * SUCH DAMAGE.
31: *
32: * @(#)dcareg.h 8.1 (Berkeley) 6/10/93
33: */
34:
35: #include <hp300/dev/iotypes.h> /* XXX */
36:
37: #ifdef hp700
38: struct dcadevice {
39: vu_char dca_reset;
40: vu_char dca_pad[0x800-1];
41: vu_char dca_data; /* receive buf or xmit hold */
42: vu_char dca_ier; /* interrupt enable */
43: vu_char dca_iir; /* (RO) interrupt identify */
44: #define dca_fifo dca_iir /* (WO) FIFO control */
45: vu_char dca_cfcr; /* line control */
46: vu_char dca_mcr; /* modem control */
47: vu_char dca_lsr; /* line status */
48: vu_char dca_msr; /* modem status */
49: vu_char dca_scr; /* scratch pad */
50: };
51: #else
52: struct dcadevice {
53: /* card registers */
54: u_char dca_pad0;
55: vu_char dca_id; /* 0x01 (read) */
56: #define dca_reset dca_id /* 0x01 (write) */
57: u_char dca_pad1;
58: vu_char dca_ic; /* 0x03 */
59: u_char dca_pad2;
60: vu_char dca_ocbrc; /* 0x05 */
61: u_char dca_pad3;
62: vu_char dca_lcsm; /* 0x07 */
63: u_char dca_pad4[8];
64: /* chip registers */
65: u_char dca_pad5;
66: vu_char dca_data; /* 0x11 */
67: u_char dca_pad6;
68: vu_char dca_ier; /* 0x13 */
69: u_char dca_pad7;
70: vu_char dca_iir; /* 0x15 (read) */
71: #define dca_fifo dca_iir /* 0x15 (write) */
72: u_char dca_pad8;
73: vu_char dca_cfcr; /* 0x17 */
74: u_char dca_pad9;
75: vu_char dca_mcr; /* 0x19 */
76: u_char dca_padA;
77: vu_char dca_lsr; /* 0x1B */
78: u_char dca_padB;
79: vu_char dca_msr; /* 0x1D */
80: };
81: #endif
82:
83: /* interface reset/id (300 only) */
84: #define DCAID0 0x02
85: #define DCAID1 0x42
86: #define DCACON 0x80 /* REMOTE/LOCAL switch */
87:
88: /* interrupt control (300 only) */
89: #define DCAIPL(x) ((((x) >> 4) & 3) + 3)
90: #define IC_IR 0x40
91: #define IC_IE 0x80
92:
93: /*
94: * 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier)
95: * NB: This constant is for a 7.3728 clock frequency. The 300 clock
96: * frequency is 2.4576, giving a constant of 153600.
97: */
98: #ifdef hp300
99: #define DCABRD(x) (153600 / (x))
100: #endif
101: #ifdef hp700
102: #define DCABRD(x) (460800 / (x))
103: #endif
104:
105: /* interrupt enable register */
106: #define IER_ERXRDY 0x1 /* Enable receiver interrupt */
107: #define IER_ETXRDY 0x2 /* Enable transmitter empty interrupt */
108: #define IER_ERLS 0x4 /* Enable line status interrupt */
109: #define IER_EMSC 0x8 /* Enable modem status interrupt */
110:
111: /* interrupt identification register */
112: #define IIR_IMASK 0xf
113: #define IIR_RXTOUT 0xc
114: #define IIR_RLS 0x6 /* Line status change */
115: #define IIR_RXRDY 0x4 /* Receiver ready */
116: #define IIR_TXRDY 0x2 /* Transmitter ready */
117: #define IIR_NOPEND 0x1 /* No pending interrupts */
118: #define IIR_MLSC 0x0 /* Modem status */
119: #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
120:
121: /* fifo control register */
122: #define FIFO_ENABLE 0x01 /* Turn the FIFO on */
123: #define FIFO_RCV_RST 0x02 /* Reset RX FIFO */
124: #define FIFO_XMT_RST 0x04 /* Reset TX FIFO */
125: #define FIFO_DMA_MODE 0x08
126: #define FIFO_TRIGGER_1 0x00 /* Trigger RXRDY intr on 1 character */
127: #define FIFO_TRIGGER_4 0x40 /* ibid 4 */
128: #define FIFO_TRIGGER_8 0x80 /* ibid 8 */
129: #define FIFO_TRIGGER_14 0xc0 /* ibid 14 */
130:
131: /* character format control register */
132: #define CFCR_DLAB 0x80
133: #define CFCR_SBREAK 0x40
134: #define CFCR_PZERO 0x30
135: #define CFCR_PONE 0x20
136: #define CFCR_PEVEN 0x10
137: #define CFCR_PODD 0x00
138: #define CFCR_PENAB 0x08
139: #define CFCR_STOPB 0x04
140: #define CFCR_8BITS 0x03
141: #define CFCR_7BITS 0x02
142: #define CFCR_6BITS 0x01
143: #define CFCR_5BITS 0x00
144:
145: /* modem control register */
146: #define MCR_LOOPBACK 0x10 /* Loop test: echos from TX to RX */
147: #define MCR_IEN 0x08 /* Out2: enables UART interrupts */
148: #define MCR_DRS 0x04 /* Out1: resets some internal modems */
149: #define MCR_RTS 0x02 /* Request To Send */
150: #define MCR_DTR 0x01 /* Data Terminal Ready */
151:
152: /* line status register */
153: #define LSR_RCV_FIFO 0x80
154: #define LSR_TSRE 0x40 /* Transmitter empty: byte sent */
155: #define LSR_TXRDY 0x20 /* Transmitter buffer empty */
156: #define LSR_BI 0x10 /* Break detected */
157: #define LSR_FE 0x08 /* Framing error: bad stop bit */
158: #define LSR_PE 0x04 /* Parity error */
159: #define LSR_OE 0x02 /* Overrun, lost incoming byte */
160: #define LSR_RXRDY 0x01 /* Byte ready in Receive Buffer */
161: #define LSR_RCV_MASK 0x1f /* Mask for incoming data or error */
162:
163: /* modem status register */
164: #define MSR_DCD 0x80 /* Current Data Carrier Detect */
165: #define MSR_RI 0x40 /* Current Ring Indicator */
166: #define MSR_DSR 0x20 /* Current Data Set Ready */
167: #define MSR_CTS 0x10 /* Current Clear to Send */
168: #define MSR_DDCD 0x08 /* DCD has changed state */
169: #define MSR_TERI 0x04 /* RI has toggled low to high */
170: #define MSR_DDSR 0x02 /* DSR has changed state */
171: #define MSR_DCTS 0x01 /* CTS has changed state */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to dcareg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / hp300 / dev