Annotation of sys/arch/aviion/stand/netboot/if_lereg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_lereg.h,v 1.1 2006/05/16 22:48:18 miod Exp $ */
2:
3: /*-
4: * Copyright (c) 1982, 1992, 1993
5: * The Regents of the University of California. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. Neither the name of the University nor the names of its contributors
16: * may be used to endorse or promote products derived from this software
17: * without specific prior written permission.
18: *
19: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29: * SUCH DAMAGE.
30: *
31: * @(#)if_lereg.h 8.2 (Berkeley) 10/30/93
32: */
33:
34: #define LEMTU 1518
35: #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */
36: #define LERBUF 8
37: #define LERBUFLOG2 3
38: #define LE_RLEN (LERBUFLOG2 << 13)
39: #define LETBUF 1
40: #define LETBUFLOG2 0
41: #define LE_TLEN (LETBUFLOG2 << 13)
42:
43: /*
44: * LANCE registers. Although there are 16 bit registers, on the AV400
45: * design, they need to be accessed as 32 bit registers. Bus magic...
46: */
47: struct lereg1 {
48: volatile u_int32_t ler1_rdp; /* register data port */
49: volatile u_int32_t ler1_rap; /* register address port */
50: };
51:
52: /* register addresses */
53: #define LE_CSR0 0 /* Control and status register */
54: #define LE_CSR1 1 /* low address of init block */
55: #define LE_CSR2 2 /* high address of init block */
56: #define LE_CSR3 3 /* Bus master and control */
57:
58: /* Control and status register 0 (csr0) */
59: #define LE_C0_ERR 0x8000 /* error summary */
60: #define LE_C0_BABL 0x4000 /* transmitter timeout error */
61: #define LE_C0_CERR 0x2000 /* collision */
62: #define LE_C0_MISS 0x1000 /* missed a packet */
63: #define LE_C0_MERR 0x0800 /* memory error */
64: #define LE_C0_RINT 0x0400 /* receiver interrupt */
65: #define LE_C0_TINT 0x0200 /* transmitter interrupt */
66: #define LE_C0_IDON 0x0100 /* initialization done */
67: #define LE_C0_INTR 0x0080 /* interrupt condition */
68: #define LE_C0_INEA 0x0040 /* interrupt enable */
69: #define LE_C0_RXON 0x0020 /* receiver on */
70: #define LE_C0_TXON 0x0010 /* transmitter on */
71: #define LE_C0_TDMD 0x0008 /* transmit demand */
72: #define LE_C0_STOP 0x0004 /* disable all external activity */
73: #define LE_C0_STRT 0x0002 /* enable external activity */
74: #define LE_C0_INIT 0x0001 /* begin initialization */
75:
76: #define LE_C0_BITS \
77: "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\
78: \12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
79:
80: /* Control and status register 3 (csr3) */
81: #define LE_C3_BSWP 0x4 /* byte swap */
82: #define LE_C3_ACON 0x2 /* ALE control, eh? */
83: #define LE_C3_BCON 0x1 /* byte control */
84: /*
85: * Current size is 13,758 bytes with 8 x 1518 receive buffers and
86: * 1 x 1518 transmit buffer.
87: */
88: struct lereg2 {
89: /* initialization block */
90: volatile u_short ler2_mode; /* mode */
91: volatile u_char ler2_padr[6]; /* physical address */
92: #ifdef new_code
93: volatile u_short ler2_ladrf[4]; /* logical address filter */
94: #else
95: volatile u_long ler2_ladrf0; /* logical address filter */
96: volatile u_long ler2_ladrf1; /* logical address filter */
97: #endif
98: volatile u_short ler2_rdra; /* receive descriptor addr */
99: volatile u_short ler2_rlen; /* rda high and ring size */
100: volatile u_short ler2_tdra; /* transmit descriptor addr */
101: volatile u_short ler2_tlen; /* tda high and ring size */
102: /* receive message descriptors. bits/hadr are byte order dependent. */
103: struct lermd {
104: volatile u_short rmd0; /* low address of packet */
105: volatile u_char rmd1_bits; /* descriptor bits */
106: volatile u_char rmd1_hadr; /* high address of packet */
107: volatile short rmd2; /* buffer byte count */
108: volatile u_short rmd3; /* message byte count */
109: } ler2_rmd[LERBUF];
110: /* transmit message descriptors */
111: struct letmd {
112: volatile u_short tmd0; /* low address of packet */
113: volatile u_char tmd1_bits; /* descriptor bits */
114: volatile u_char tmd1_hadr; /* high address of packet */
115: volatile short tmd2; /* buffer byte count */
116: volatile u_short tmd3; /* transmit error bits */
117: } ler2_tmd[LETBUF];
118: volatile char ler2_rbuf[LERBUF][LEMTU];
119: volatile char ler2_tbuf[LETBUF][LEMTU];
120: };
121: /* Initialzation block (mode) */
122: #define LE_MODE_PROM 0x8000 /* promiscuous mode */
123: /* 0x7f80 reserved, must be zero */
124: #define LE_MODE_INTL 0x0040 /* internal loopback */
125: #define LE_MODE_DRTY 0x0020 /* disable retry */
126: #define LE_MODE_COLL 0x0010 /* force a collision */
127: #define LE_MODE_DTCR 0x0008 /* disable transmit CRC */
128: #define LE_MODE_LOOP 0x0004 /* loopback mode */
129: #define LE_MODE_DTX 0x0002 /* disable transmitter */
130: #define LE_MODE_DRX 0x0001 /* disable receiver */
131: #define LE_MODE_NORMAL 0 /* none of the above */
132:
133:
134: /* Receive message descriptor 1 (rmd1_bits) */
135: #define LE_R1_OWN 0x80 /* LANCE owns the packet */
136: #define LE_R1_ERR 0x40 /* error summary */
137: #define LE_R1_FRAM 0x20 /* framing error */
138: #define LE_R1_OFLO 0x10 /* overflow error */
139: #define LE_R1_CRC 0x08 /* CRC error */
140: #define LE_R1_BUFF 0x04 /* buffer error */
141: #define LE_R1_STP 0x02 /* start of packet */
142: #define LE_R1_ENP 0x01 /* end of packet */
143:
144: #define LE_R1_BITS \
145: "\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP"
146:
147: /* Transmit message descriptor 1 (tmd1_bits) */
148: #define LE_T1_OWN 0x80 /* LANCE owns the packet */
149: #define LE_T1_ERR 0x40 /* error summary */
150: #define LE_T1_MORE 0x10 /* multiple collisions */
151: #define LE_T1_ONE 0x08 /* single collision */
152: #define LE_T1_DEF 0x04 /* defferred transmit */
153: #define LE_T1_STP 0x02 /* start of packet */
154: #define LE_T1_ENP 0x01 /* end of packet */
155:
156: #define LE_T1_BITS \
157: "\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP"
158:
159: /* Transmit message descriptor 3 (tmd3) */
160: #define LE_T3_BUFF 0x8000 /* buffer error */
161: #define LE_T3_UFLO 0x4000 /* underflow error */
162: #define LE_T3_LCOL 0x1000 /* late collision */
163: #define LE_T3_LCAR 0x0800 /* loss of carrier */
164: #define LE_T3_RTRY 0x0400 /* retry error */
165: #define LE_T3_TDR_MASK 0x03ff /* time domain reflectometry counter */
166:
167: #define LE_XMD2_ONES 0xf000
168:
169: #define LE_T3_BITS \
170: "\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY"
171:
172:
173: #define LE_ADDR_LOW_MASK (0xffff)
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to if_lereg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / aviion / stand / netboot