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Annotation of sys/arch/aviion/include/avcommon.h, Revision 1.1

1.1     ! nbrk        1: /*     $OpenBSD: avcommon.h,v 1.2 2006/05/21 22:43:54 miod Exp $       */
        !             2: /*
        !             3:  * Copyright (c) 1999 Steve Murphree, Jr.
        !             4:  * All rights reserved.
        !             5:  *
        !             6:  * Redistribution and use in source and binary forms, with or without
        !             7:  * modification, are permitted provided that the following conditions
        !             8:  * are met:
        !             9:  * 1. Redistributions of source code must retain the above copyright
        !            10:  *    notice, this list of conditions and the following disclaimer.
        !            11:  * 2. Redistributions in binary form must reproduce the above copyright
        !            12:  *    notice, this list of conditions and the following disclaimer in the
        !            13:  *    documentation and/or other materials provided with the distribution.
        !            14:  * 3. All advertising materials mentioning features or use of this software
        !            15:  *    must display the following acknowledgement:
        !            16:  *      This product includes software developed by Steve Murphree, Jr.
        !            17:  * 4. The name of the author may not be used to endorse or promote products
        !            18:  *    derived from this software without specific prior written permission
        !            19:  *
        !            20:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
        !            21:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
        !            22:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
        !            23:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
        !            24:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
        !            25:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
        !            26:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
        !            27:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
        !            28:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
        !            29:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
        !            30:  *
        !            31:  */
        !            32: /*
        !            33:  * Mach Operating System
        !            34:  * Copyright (c) 1991 Carnegie Mellon University
        !            35:  * Copyright (c) 1991 OMRON Corporation
        !            36:  * All Rights Reserved.
        !            37:  *
        !            38:  * Permission to use, copy, modify and distribute this software and its
        !            39:  * documentation is hereby granted, provided that both the copyright
        !            40:  * notice and this permission notice appear in all copies of the
        !            41:  * software, derivative works or modified versions, and any portions
        !            42:  * thereof, and that both notices appear in supporting documentation.
        !            43:  *
        !            44:  */
        !            45:
        !            46: #ifndef        __MACHINE_AVCOMMON_H__
        !            47: #define        __MACHINE_AVCOMMON_H__
        !            48:
        !            49: /*
        !            50:  * Common declarations for hardware level device registers and such,
        !            51:  * for 88100-based designs.
        !            52:  */
        !            53:
        !            54: /* per-processor interrupt enable registers */
        !            55: #define        AV_IEN_BASE     0xfff84000
        !            56: #define        AV_IEN0         0xfff84004      /* interrupt enable CPU 0 */
        !            57: #define        AV_IEN1         0xfff84008      /* interrupt enable CPU 1 */
        !            58: #define        AV_IEN2         0xfff84010      /* interrupt enable CPU 2 */
        !            59: #define        AV_IEN3         0xfff84020      /* interrupt enable CPU 3 */
        !            60: #define        AV_IENALL       0xfff8403c      /* simultaneous write */
        !            61: #define        AV_IEN(cpu)     (AV_IEN_BASE + (4 << (cpu)))
        !            62:
        !            63: #define        AV_IST          0xfff84040      /* interrupt status register */
        !            64:
        !            65: #define INT_LEVEL              8               /* # of interrupt level + 1 */
        !            66: #define ISR_GET_CURRENT_MASK(cpu) \
        !            67:        (*(volatile u_int *)AV_IST & int_mask_reg[cpu])
        !            68:
        !            69: #define        AV_ISTATE       0xfff84088      /* HW interrupt status */
        !            70: #define        AV_CLRINT       0xfff8408c      /* reset HW interrupt */
        !            71:
        !            72: #define        AV_GCSR         0xfff86000      /* global control and status reg */
        !            73: #define AV_GLOBAL0     0xfff86001      /* global control and status regs */
        !            74: #define AV_GLOBAL1     0xfff86003
        !            75: #define        AV_LRST                 0x80
        !            76: #define        AV_SYSCON               0x40
        !            77: #define AV_BRDID       0xfff86005
        !            78: #define AV_CGCSR0      0xfff86007
        !            79: #define AV_CGCSR1      0xfff86009
        !            80: #define AV_CGCSR2      0xfff8600b
        !            81: #define AV_CGCSR3      0xfff8600d
        !            82: #define AV_CGCSR4      0xfff8600f
        !            83: #define        AV_UCSR         0xfff87000      /* utility control and status reg */
        !            84: #define        AV_BASAD        0xfff87004      /* base address reg */
        !            85: #define        AV_GLBRES       0xfff8700c      /* global reset reg */
        !            86:
        !            87: #define        AV_CCSR         0xfff88000      /* CPU board control status reg */
        !            88: #define        AV_ERROR        0xfff88004      /* Mbus fault reg */
        !            89: #define        AV_PCNFA        0xfff88008      /* Pbus A decoder reg */
        !            90: #define        AV_PCNFB        0xfff8800c      /* Pbus B decoder reg */
        !            91: #define        AV_EXTAD        0xfff88010      /* A24 master A24-A31 addr reg */
        !            92: #define        AV_EXTAM        0xfff88014      /* AM3-AM0 addr modifiers reg */
        !            93: #define        AV_WHOAMI       0xfff88018      /* whoami reg */
        !            94: #define        AV_WMAD         0xfff88020      /* write mbus addr decoder reg */
        !            95: #define        AV_RMAD         0xfff88024      /* read mbus addr decoder reg */
        !            96: #define        AV_WVAD         0xfff88028      /* write vmebus addr decoder reg */
        !            97: #define        AV_RVAD         0xfff8802c      /* read vmebus adds decoder reg */
        !            98:
        !            99: /*
        !           100:  * ISTATE and CLRINT register bits
        !           101:  */
        !           102:
        !           103: #define ISTATE_ABORT           0x04
        !           104: #define        ISTATE_ACFAIL           0x02
        !           105: #define        ISTATE_SYSFAIL          0x01
        !           106:
        !           107: /*
        !           108:  * UCSR register bits
        !           109:  */
        !           110:
        !           111: #define UCSR_PWRUPBIT  0x00004000      /* powerup indicator */
        !           112: #define UCSR_DRVSFBIT  0x00002000      /* Board system fail */
        !           113: #define UCSR_BRIRQBIT  0x00001000      /* drives VME IRQ1 broadcast int */
        !           114: #define UCSR_ROBINBIT  0x00000800      /* sel round robin VME arbiter mode */
        !           115: #define UCSR_BRLVBITS  0x00000600      /* VME bus request level 0-3 */
        !           116: #define UCSR_RNEVERBIT  0x00000100     /* VME bus never release once req'd */
        !           117: #define UCSR_RONRBIT   0x00000080      /* VME bus req release on no request */
        !           118: #define UCSR_RWDBIT    0x00000040      /* VME bus request release when done */
        !           119: #define UCSR_EARBTOBIT  0x00000020     /* enable VME arbiter bus timeout */
        !           120: #define VTOSELBITS     0x00000018      /* VMEbus timeout select bits */
        !           121: #define VTO32US                        0x00    /* 32 usec */
        !           122: #define VTO64US                        0x01    /* 64 usec */
        !           123: #define VTO128US               0x10    /* 128 usec */
        !           124: #define VTODISABLE             0x18    /* disabled */
        !           125:
        !           126: /* these are the various Z8536 CIO counter/timer registers */
        !           127: #define CIO_BASE               0xfff83000
        !           128: #define CIO_PORTC              0xfff83000
        !           129: #define CIO_PORTB              0xfff83004
        !           130: #define CIO_PORTA              0xfff83008
        !           131: #define CIO_CTRL               0xfff8300c
        !           132:
        !           133: #define CIO_MICR               0x00    /* Master interrupt control register */
        !           134: #define CIO_MICR_MIE           0x80
        !           135: #define CIO_MICR_DLC           0x40
        !           136: #define CIO_MICR_NV            0x20
        !           137: #define CIO_MICR_PAVIS         0x10
        !           138: #define CIO_MICR_PBVIS         0x08
        !           139: #define CIO_MICR_CTVIS         0x04
        !           140: #define CIO_MICR_RJA           0x02
        !           141: #define CIO_MICR_RESET         0x01
        !           142:
        !           143: #define CIO_MCCR               0x01    /* Master config control register */
        !           144: #define CIO_MCCR_PBE           0x80
        !           145: #define CIO_MCCR_CT1E          0x40
        !           146: #define CIO_MCCR_CT2E          0x20
        !           147: #define CIO_MCCR_CT3E          0x10
        !           148: #define CIO_MCCR_PLC           0x08
        !           149: #define CIO_MCCR_PAE           0x04
        !           150:
        !           151: #define CIO_CTMS1              0x1c    /* Counter/timer mode specification #1 */
        !           152: #define CIO_CTMS2              0x1d    /* Counter/timer mode specification #2 */
        !           153: #define CIO_CTMS3              0x1e    /* Counter/timer mode specification #3 */
        !           154: #define CIO_CTMS_CSC           0x80    /* Continuous Single Cycle */
        !           155: #define CIO_CTMS_EOE           0x40    /* External Output Enable  */
        !           156: #define CIO_CTMS_ECE           0x20    /* External Count Enable   */
        !           157: #define CIO_CTMS_ETE           0x10    /* External Trigger Enable */
        !           158: #define CIO_CTMS_EGE           0x08    /* External Gate Enable    */
        !           159: #define CIO_CTMS_REB           0x04    /* Retrigger Enable Bit    */
        !           160: #define CIO_CTMS_PO            0x00    /* Pulse Output            */
        !           161: #define CIO_CTMS_OSO           0x01    /* One Shot Output         */
        !           162: #define CIO_CTMS_SWO           0x02    /* Square Wave Output      */
        !           163:
        !           164: #define CIO_IVR                        0x04    /* Interrupt vector register */
        !           165:
        !           166: #define CIO_CSR1               0x0a    /* Command and status register CTC #1 */
        !           167: #define CIO_CSR2               0x0b    /* Command and status register CTC #2 */
        !           168: #define CIO_CSR3               0x0c    /* Command and status register CTC #3 */
        !           169:
        !           170: #define CIO_CT1MSB             0x16    /* CTC #1 Timer constant - MSB */
        !           171: #define CIO_CT1LSB             0x17    /* CTC #1 Timer constant - LSB */
        !           172: #define CIO_CT2MSB             0x18    /* CTC #2 Timer constant - MSB */
        !           173: #define CIO_CT2LSB             0x19    /* CTC #2 Timer constant - LSB */
        !           174: #define CIO_CT3MSB             0x1a    /* CTC #3 Timer constant - MSB */
        !           175: #define CIO_CT3LSB             0x1b    /* CTC #3 Timer constant - LSB */
        !           176: #define CIO_PDCA               0x23    /* Port A data direction control */
        !           177: #define CIO_PDCB               0x2b    /* Port B data direction control */
        !           178:
        !           179: #define CIO_GCB                        0x04    /* CTC Gate command bit */
        !           180: #define CIO_TCB                        0x02    /* CTC Trigger command bit */
        !           181: #define CIO_IE                 0xc0    /* CTC Interrupt enable (set) */
        !           182: #define CIO_CIP                        0x20    /* CTC Clear interrupt pending */
        !           183: #define CIO_IP                 0x20    /* CTC Interrupt pending */
        !           184:
        !           185: #endif /* __MACHINE_AVCOMMON_H__ */

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