Annotation of sys/arch/aviion/include/av400.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: av400.h,v 1.3 2006/05/21 12:22:03 miod Exp $ */
! 2: /*
! 3: * Copyright (c) 1999 Steve Murphree, Jr.
! 4: * All rights reserved.
! 5: *
! 6: * Redistribution and use in source and binary forms, with or without
! 7: * modification, are permitted provided that the following conditions
! 8: * are met:
! 9: * 1. Redistributions of source code must retain the above copyright
! 10: * notice, this list of conditions and the following disclaimer.
! 11: * 2. Redistributions in binary form must reproduce the above copyright
! 12: * notice, this list of conditions and the following disclaimer in the
! 13: * documentation and/or other materials provided with the distribution.
! 14: * 3. All advertising materials mentioning features or use of this software
! 15: * must display the following acknowledgement:
! 16: * This product includes software developed by Steve Murphree, Jr.
! 17: * 4. The name of the author may not be used to endorse or promote products
! 18: * derived from this software without specific prior written permission
! 19: *
! 20: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 21: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 22: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 23: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 24: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 25: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 26: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 27: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 28: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 29: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 30: *
! 31: */
! 32: /*
! 33: * Mach Operating System
! 34: * Copyright (c) 1991 Carnegie Mellon University
! 35: * Copyright (c) 1991 OMRON Corporation
! 36: * All Rights Reserved.
! 37: *
! 38: * Permission to use, copy, modify and distribute this software and its
! 39: * documentation is hereby granted, provided that both the copyright
! 40: * notice and this permission notice appear in all copies of the
! 41: * software, derivative works or modified versions, and any portions
! 42: * thereof, and that both notices appear in supporting documentation.
! 43: *
! 44: */
! 45:
! 46: #ifndef __MACHINE_AV400_H__
! 47: #define __MACHINE_AV400_H__
! 48:
! 49: #define AV400_PROM 0xffc00000
! 50: #define AV400_PROM_SIZE 0x00200000
! 51: #define AV400_SRAM 0xffe00000
! 52: #define AV400_SRAM_SIZE 0x00020000
! 53: #define AV400_UTILITY 0xfff00000
! 54: #define AV400_UTILITY_SIZE 0x00100000
! 55:
! 56: /*
! 57: * AV400 VME mappings
! 58: */
! 59:
! 60: #define AV400_VME32_BASE 0x00000000
! 61: #define AV400_VME32_START1 0x10000000
! 62: #define AV400_VME32_END1 0x7fffffff
! 63: #define AV400_VME32_START2 0x90000000
! 64: #define AV400_VME32_END2 0xfdffffff
! 65: #define AV400_VME24_BASE 0xfe000000
! 66: #define AV400_VME24_START 0x00000000
! 67: #define AV400_VME24_END 0x00ffffff
! 68: #define AV400_VME16_BASE 0xffff0000
! 69: #define AV400_VME16_START 0x00000000
! 70: #define AV400_VME16_END 0x0000ffff
! 71:
! 72: #define AV400_ISVMEA32(addr) \
! 73: (((addr) >= AV400_VME32_START1 && (addr) < AV400_VME32_END1 + 1U) || \
! 74: ((addr) >= AV400_VME32_START2 && (addr) < AV400_VME32_END2 + 1U))
! 75: #define AV400_ISVMEA24(addr) \
! 76: ((addr) >= AV400_VME24_START && (addr) < AV400_VME24_END + 1U)
! 77: #define AV400_ISVMEA16(addr) \
! 78: ((addr) >= AV400_VME16_START /* && (addr) <= AV400_VME16_END */)
! 79:
! 80: /*
! 81: * AV400 declarations for hardware level device registers and such.
! 82: */
! 83:
! 84: #define AV400_SETSWI 0xfff84080 /* generate soft interrupt */
! 85: #define AV400_CLRSWI 0xfff84084 /* reset soft interrupt */
! 86:
! 87: #define AV400_VIRQLV 0xfff85000
! 88: #define AV400_VIACK1V 0xfff85004
! 89: #define AV400_VIACK2V 0xfff85008
! 90: #define AV400_VIACK3V 0xfff8500c
! 91: #define AV400_VIACK4V 0xfff85010
! 92: #define AV400_VIACK5V 0xfff85014
! 93: #define AV400_VIACK6V 0xfff85018
! 94: #define AV400_VIACK7V 0xfff8501c
! 95: #define AV400_VIRQV 0xfff85020
! 96: #define AV400_IVEC 0x40 /* vector returned upon AV400 int */
! 97:
! 98: /*
! 99: * IEN and IST register bits
! 100: * See ``Programming System control and I/O registers for the 100, 200, 300,
! 101: * 400, 3000 and 4000 series'', section 3 (Interrupts).
! 102: */
! 103:
! 104: #define IRQ_RESERVED 0x1800018c /* all reserved bits */
! 105: #define IRQ_ABORT 0x80000000 /* 31 - Abort */
! 106: #define IRQ_ACF 0x40000000 /* 30 - AC Fail */
! 107: #define IRQ_ARBTO 0x20000000 /* 29 - VME Arbiter Timeout */
! 108: #define IRQ_ZBUF 0x04000000 /* 26 - Z Buffer */
! 109: #define IRQ_VID 0x02000000 /* 25 - Video */
! 110: #define IRQ_PAR 0x01000000 /* 24 - Parity Error */
! 111: #define IRQ_VME7 0x00800000 /* 23 - VMEBus level 7 */
! 112: #define IRQ_KBD 0x00400000 /* 22 - Keyboard */
! 113: #define IRQ_CIOI 0x00200000 /* 21 - CIO */
! 114: #define IRQ_SF 0x00100000 /* 20 - System Failure */
! 115: #define IRQ_VME6 0x00080000 /* 19 - VMEBus level 6 */
! 116: #define IRQ_PPI 0x00040000 /* 18 - Parallel Port */
! 117: #define IRQ_DI1 0x00020000 /* 17 - DUART1 */
! 118: #define IRQ_DI2 0x00010000 /* 16 - DUART2 */
! 119: #define IRQ_ECI 0x00008000 /* 15 - Ethernet Controller */
! 120: #define IRQ_VME5 0x00004000 /* 14 - VMEBus level 5 */
! 121: #define IRQ_DTC 0x00002000 /* 13 - DMA Terminal Count */
! 122: #define IRQ_VME4 0x00001000 /* 12 - VMEBus level 4 */
! 123: #define IRQ_DWP 0x00000800 /* 11 - DMA Write Protect */
! 124: #define IRQ_VME3 0x00000400 /* 10 - VMEBus level 3 */
! 125: #define IRQ_DVB 0x00000200 /* 09 - DMA Valid Bit */
! 126: #define IRQ_VME2 0x00000040 /* 06 - VMEBus level 2 */
! 127: #define IRQ_SCI 0x00000020 /* 05 - SCSI Controller */
! 128: #define IRQ_VME1 0x00000010 /* 04 - VMEBus level 1 */
! 129: #define IRQ_SWI1 0x00000002 /* 01 - SW Interrupt level 1 */
! 130: #define IRQ_SWI0 0x00000001 /* 00 - SW Interrupt level 0 */
! 131:
! 132: #define IST_STRING "\20" \
! 133: "\40ABRT\37ACF\36ARBTO\33ZBUF\32VID\31PAR" \
! 134: "\30IRQ7\27KBD\26CIOI\25SF\24IRQ6\23PPI\22DI1\21DI2" \
! 135: "\20ECI\17IRQ5\16DTC\15IRQ4\14DWP\13IRQ3\12DVB" \
! 136: "\7IRQ2\6SCI\5IRQ1\2SWI1\1SWI0"
! 137:
! 138: /* groups by function */
! 139:
! 140: /* hardware irq bits */
! 141: #define HW_FAILURE_MASK (IRQ_ABORT | IRQ_ACF | IRQ_ARBTO | IRQ_SF | \
! 142: IRQ_PAR)
! 143: /* software irq bits */
! 144: #define SOFT_INTERRUPT_MASK (IRQ_SWI1 | IRQ_SWI0)
! 145: /* VME irq bits */
! 146: #define VME_INTERRUPT_MASK (IRQ_VME7 | IRQ_VME6 | IRQ_VME5 | IRQ_VME4 | \
! 147: IRQ_VME3 | IRQ_VME2 | IRQ_VME1)
! 148: /* on-board irq bits */
! 149: #define OBIO_INTERRUPT_MASK (IRQ_ZBUF | IRQ_VID | IRQ_KBD | IRQ_CIOI | \
! 150: IRQ_PPI | IRQ_DI1 | IRQ_DI2 | IRQ_ECI | \
! 151: IRQ_DTC | IRQ_DWP | IRQ_DVB | IRQ_SCI)
! 152:
! 153: /* groups by interrupt levels */
! 154: /* we do not enable and define levels yet for: ZBUF, VID, KBD, PPI, SCI, DMA */
! 155:
! 156: #define LVL7 (IRQ_ABORT | IRQ_ACF | IRQ_VME7 | IRQ_SF)
! 157: #define LVL6 (IRQ_VME6)
! 158: #define LVL5 (IRQ_VME5 | IRQ_CIOI)
! 159: #define LVL4 (IRQ_VME4)
! 160: #define LVL3 (IRQ_VME3 | IRQ_DI1 | IRQ_DI2)
! 161: #define LVL2 (IRQ_VME2) /* | IRQ_SCI */
! 162: #define LVL1 (IRQ_VME1 | IRQ_ECI )
! 163: #define LVL0 (0x0)
! 164:
! 165: /* interrupts we want to process on the master CPU only */
! 166: #define SLAVE_MASK (HW_FAILURE_MASK | OBIO_INTERRUPT_MASK)
! 167:
! 168: #define MASK_LVL_0 (LVL7 | LVL6 | LVL5 | LVL4 | LVL3 | LVL2 | LVL1)
! 169: #define MASK_LVL_1 (LVL7 | LVL6 | LVL5 | LVL4 | LVL3 | LVL2)
! 170: #define MASK_LVL_2 (LVL7 | LVL6 | LVL5 | LVL4 | LVL3)
! 171: #define MASK_LVL_3 (LVL7 | LVL6 | LVL5 | LVL4)
! 172: #define MASK_LVL_4 (LVL7 | LVL6 | LVL5)
! 173: #define MASK_LVL_5 (LVL7 | LVL6)
! 174: #define MASK_LVL_6 (LVL7)
! 175: #define MASK_LVL_7 (IRQ_ABORT)
! 176:
! 177: #define DART_BASE 0xfff82000
! 178:
! 179: /*
! 180: * CMMU addresses
! 181: */
! 182:
! 183: #define AV400_CMMU_D0 0xfff00000
! 184: #define AV400_CMMU_I0 0xfff01000
! 185: #define AV400_CMMU_D1 0xfff02000
! 186: #define AV400_CMMU_I1 0xfff03000
! 187: #define AV400_CMMU_D2 0xfff04000
! 188: #define AV400_CMMU_I2 0xfff05000
! 189: #define AV400_CMMU_D3 0xfff06000
! 190: #define AV400_CMMU_I3 0xfff07000
! 191:
! 192: #endif /* __MACHINE_AV400_H__ */
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