Annotation of sys/arch/aviion/dev/dartreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: dartreg.h,v 1.1.1.1 2006/05/09 18:24:15 miod Exp $ */
! 2:
! 3: #define MAXPORTS 2 /* max count of PORTS/DUART */
! 4:
! 5: #define A_PORT 0 /* flag for port a */
! 6: #define B_PORT 1 /* flag for port b */
! 7:
! 8: /* the access to the same command register must be delayed,
! 9: because the chip has some hardware problems in this case */
! 10: #define DELAY_CR do { volatile int i; for (i = 0; i < 250; ++i); } while (0)
! 11:
! 12: /*********************** MC68681 DEFINITIONS ************************/
! 13:
! 14: /* mode register 1: MR1x operations */
! 15: #define RXRTS 0x80 /* enable receiver RTS */
! 16: #define PAREN 0x00 /* with parity */
! 17: #define PARDIS 0x10 /* no parity */
! 18: #define EVENPAR 0x00 /* even parity */
! 19: #define ODDPAR 0x04 /* odd parity */
! 20: #define CL5 0x00 /* 5 bits per char */
! 21: #define CL6 0x01 /* 6 bits per char */
! 22: #define CL7 0x02 /* 7 bits per char */
! 23: #define CL8 0x03 /* 8 bits per char */
! 24: #define PARMODEMASK 0x18 /* parity mode mask */
! 25: #define PARTYPEMASK 0x04 /* parity type mask */
! 26: #define CLMASK 0x03 /* character length mask */
! 27:
! 28: /* mode register 2: MR2x operations */
! 29: #define TXRTS 0x20 /* enable transmitter RTS */
! 30: #define TXCTS 0x10 /* enable transmitter CTS */
! 31: #define SB2 0x0f /* 2 stop bits */
! 32: #define SB1 0x07 /* 1 stop bit */
! 33: #define SB1L5 0x00 /* 1 stop bit at 5 bits per character */
! 34:
! 35: #define SBMASK 0x0f /* stop bit mask */
! 36:
! 37: /* clock-select register: CSRx operations */
! 38: #define NOBAUD -1 /* 50 and 200 baud are not possible */
! 39: /* they are not in Baud register set 2 */
! 40: #define BD75 0x00 /* 75 baud */
! 41: #define BD110 0x11 /* 110 baud */
! 42: #define BD134 0x22 /* 134.5 baud */
! 43: #define BD150 0x33 /* 150 baud */
! 44: #define BD300 0x44 /* 300 baud */
! 45: #define BD600 0x55 /* 600 baud */
! 46: #define BD1200 0x66 /* 1200 baud */
! 47: #define BD1800 0xaa /* 1800 baud */
! 48: #define BD2400 0x88 /* 2400 baud */
! 49: #define BD4800 0x99 /* 4800 baud */
! 50: #define BD9600 0xbb /* 9600 baud */
! 51: #define BD19200 0xcc /* 19200 baud */
! 52:
! 53: #define DEFBAUD BD9600 /* default value if baudrate is not possible */
! 54:
! 55:
! 56: /* channel command register: CRx operations */
! 57: #define MRRESET 0x10 /* reset mr pointer to mr1 */
! 58: #define RXRESET 0x20 /* reset receiver */
! 59: #define TXRESET 0x30 /* reset transmitter */
! 60: #define ERRRESET 0x40 /* reset error status */
! 61: #define BRKINTRESET 0x50 /* reset channel's break interrupt */
! 62: #define BRKSTART 0x60 /* start break */
! 63: #define BRKSTOP 0x70 /* stop break */
! 64: #define TXDIS 0x08 /* disable transmitter */
! 65: #define TXEN 0x04 /* enable transmitter */
! 66: #define RXDIS 0x02 /* disable receiver */
! 67: #define RXEN 0x01 /* enable receiver */
! 68:
! 69: /* status register: SRx status */
! 70: #define RBRK 0x80 /* received break */
! 71: #define FRERR 0x40 /* frame error */
! 72: #define PERR 0x20 /* parity error */
! 73: #define ROVRN 0x10 /* receiver overrun error */
! 74: #define TXEMT 0x08 /* transmitter empty */
! 75: #define TXRDY 0x04 /* transmitter ready */
! 76: #define FFULL 0x02 /* receiver FIFO full */
! 77: #define RXRDY 0x01 /* receiver ready */
! 78:
! 79: /* output port configuration register: OPCR operations */
! 80: #define OPSET 0x00 /* set all op lines to op function */
! 81: #define OPSETTO 0x04 /* use OP3 for timer output */
! 82:
! 83: /* output port register: OP operations */
! 84: #define OPDTRB 0x20 /* DTR line output b on the VME188, 181, 141 */
! 85: #define OPDTRA 0x04 /* DTR line output a */
! 86: #define OPRTSB 0x02 /* RTS line output b */
! 87: #define OPRTSA 0x01 /* RTS line output a */
! 88:
! 89: /* auxiliary control register: ACR operations */
! 90: #define BDSET1 0x00 /* baudrate generator set 1 */
! 91: #define BDSET2 0x80 /* baudrate generator set 2 */
! 92: #define CCLK1 0x60 /* timer clock: external rate. TA */
! 93: #define CCLK16 0x30 /* counter clock: x1 clk divided by 16 */
! 94: #define SLCTIM 0x7800/* timer count to get 60 Hz time slice (16.6ms ticks) */
! 95: #define IPDCDIB 0x08 /* IP3 change == DCD input on port B */
! 96: #define IPDCDIA 0x04 /* IP2 change == DCD input on port A */
! 97:
! 98: /* input port change register: IPCR operations */
! 99: #define IPCRDCDB 0x80 /* IP3 change == DCD change on port B */
! 100: #define IPCRDCDA 0x40 /* IP2 change == DCD change on port A */
! 101:
! 102: /* Defines for mvme335 */
! 103: #define IPDCDB 0x20 /* DCD line input b */
! 104: #define IPDCDA 0x10 /* DCD line input a */
! 105:
! 106: #define IPDSRB 0x08 /* DSR line input b */
! 107: #define IPDSRA 0x04 /* DSR line input a */
! 108: #define IPCTSB 0x02 /* CTS line input b */
! 109: #define IPCTSA 0x01 /* CTS line input a */
! 110:
! 111: /* interrupt status and mask register: ISR status and IMR mask */
! 112: #define IIPCHG 0x80 /* input port change */
! 113: #define IBRKB 0x40 /* delta break b */
! 114: #define IRXRDYB 0x20 /* receiver ready b */
! 115: #define ITXRDYB 0x10 /* transmitter ready b */
! 116: #define ITIMER 0x08 /* Enable timer interrupts. */
! 117: #define IBRKA 0x04 /* delta break a */
! 118: #define IRXRDYA 0x02 /* receiver ready a */
! 119: #define ITXRDYA 0x01 /* transmitter ready a */
! 120:
! 121: /* interrupts from port a or b */
! 122: #define AINTPORT ( IRXRDYA | ITXRDYA )
! 123: #define BINTPORT ( IRXRDYB | ITXRDYB )
! 124:
! 125: /* HW write register index for ut_wr_regs[] */
! 126: #define MR1A 0 /* mode register 1 a */
! 127: #define CSRA 1 /* clock-select register a*/
! 128: #define CRA 2 /* command register a */
! 129: #define TBA 3 /* transmitter buffer a */
! 130: #define ACR 4 /* auxiliary control register*/
! 131: #define IMR 5 /* interrupt mask register */
! 132: #define CTUR 6 /* counter/timer upper reg */
! 133: #define CTLR 7 /* counter/timer lower reg */
! 134: #define MR1B 8 /* mode register 1 b */
! 135: #define CSRB 9 /* clock-select register b*/
! 136: #define CRB 10 /* command register b */
! 137: #define TBB 11 /* transmitter buffer b */
! 138: #define IVR 12 /* interrupt vector register */
! 139: #define OPCR 13 /* output port config reg */
! 140: #define OPRSET 14 /* output port: bit set cmd */
! 141: #define OPRRESET 15 /* output port: bit reset cmd */
! 142: #define MR2A 16 /* mode register 2 a */
! 143: #define MR2B 17 /* mode register 2 b */
! 144: #define MAXREG 18 /* max count of registers */
! 145:
! 146: /*
! 147: * MC68681 hardware registers.
! 148: */
! 149:
! 150: #define DART_MR1A 0x00 /* RW: mode register A */
! 151: #define DART_MR2A 0x00 /* RW: mode register A */
! 152: #define DART_SRA 0x01 /* R: status register A */
! 153: #define DART_CSRA 0x01 /* W: clock select register A */
! 154: #define DART_CRA 0x02 /* W: command register A */
! 155: #define DART_RBA 0x03 /* R: receiver buffer A */
! 156: #define DART_TBA 0x03 /* W: transmit buffer A */
! 157: #define DART_IPCR 0x04 /* R: input port change register */
! 158: #define DART_ACR 0x04 /* W: auxiliary control register */
! 159: #define DART_ISR 0x05 /* R: interrupt status register */
! 160: #define DART_IMR 0x05 /* W: interrupt mask register */
! 161: #define DART_CUR 0x06 /* R: count upper register */
! 162: #define DART_CTUR 0x06 /* W: counter/timer upper register */
! 163: #define DART_CLR 0x07 /* R: count lower register */
! 164: #define DART_CTLR 0x07 /* W: counter/timer lower register */
! 165: #define DART_MR1B 0x08 /* RW: mode register B */
! 166: #define DART_MR2B 0x08 /* RW: mode register B */
! 167: #define DART_SRB 0x09 /* R: status register B */
! 168: #define DART_CSRB 0x09 /* W: clock select register B */
! 169: #define DART_CRB 0x0a /* W: command register B */
! 170: #define DART_RBB 0x0b /* R: receiver buffer B */
! 171: #define DART_TBB 0x0b /* W: transmit buffer B */
! 172: #define DART_IVR 0x0c /* RW: interrupt vector register */
! 173: #define DART_IP 0x0d /* R: input port (unlatched) */
! 174: #define DART_OPCR 0x0d /* W: output port configuration register */
! 175: #define DART_CTSTART 0x0e /* R: start counter command */
! 176: #define DART_OPRS 0x0e /* W: output port bit set */
! 177: #define DART_CTSTOP 0x0f /* R: stop counter command */
! 178: #define DART_OPRR 0x0f /* W: output port bit reset */
! 179:
! 180: #define DART_A_BASE 0x00
! 181: #define DART_B_BASE 0x08
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