Annotation of sys/arch/armish/stand/boot/wdvar.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: wdvar.h,v 1.2 2006/07/29 15:01:49 kettenis Exp $ */
2: /* $NetBSD: wdvar.h,v 1.6 2005/12/11 12:17:06 christos Exp $ */
3:
4: /*-
5: * Copyright (c) 2003 The NetBSD Foundation, Inc.
6: * Copyright (c) 2001 Dynarc AB, Sweden. All rights reserved.
7: *
8: * This code is derived from software written by Anders Magnusson,
9: * ragge@ludd.luth.se
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. The name of the author may not be used to endorse or promote products
20: * derived from this software without specific prior written permission
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32: */
33:
34: #ifndef _STAND_WDVAR_H
35: #define _STAND_WDVAR_H
36:
37: #include <sys/disklabel.h>
38:
39: #include <dev/ic/wdcreg.h>
40: #include <dev/ata/atareg.h>
41: #include <dev/pci/pciidereg.h>
42:
43: /*
44: * WD1003 / ATA Disk Controller register definitions.
45: */
46:
47: /* offsets of registers in the 'regular' register region */
48: #define wd_data 0 /* data register (R/W - 16 bits) */
49: #define wd_error 1 /* error register (R) */
50: #define wd_precomp 1 /* write precompensation (W) */
51: #define wd_seccnt 2 /* sector count (R/W) */
52: #define wd_ireason 2 /* interrupt reason (R/W) (for atapi) */
53: #define wd_sector 3 /* first sector number (R/W) */
54: #define wd_cyl_lo 4 /* cylinder address, low byte (R/W) */
55: #define wd_cyl_hi 5 /* cylinder address, high byte (R/W) */
56: #define wd_sdh 6 /* sector size/drive/head (R/W) */
57: #define wd_command 7 /* command register (W) */
58: #define wd_lba_lo 3 /* lba address, low byte (RW) */
59: #define wd_lba_mi 4 /* lba address, middle byte (RW) */
60: #define wd_lba_hi 5 /* lba address, high byte (RW) */
61:
62: /* "shadow" registers; these may or may not overlap regular registers */
63: #define wd_status 8 /* immediate status (R) */
64: #define wd_features 9 /* features (W) */
65:
66: /* offsets of registers in the auxiliary register region */
67: #define wd_aux_altsts 0 /* alternate fixed disk status (R) */
68: #define wd_aux_ctlr 0 /* fixed disk controller control (W) */
69: #define WDCTL_4BIT 0x08 /* use four head bits (wd1003) */
70: #define WDCTL_RST 0x04 /* reset the controller */
71: #define WDCTL_IDS 0x02 /* disable controller interrupts */
72:
73: #define WDC_TIMEOUT 2000000
74: #define PCIIDE_CHANNEL_NDEV 2
75: #define NUNITS (PCIIDE_CHANNEL_NDEV * PCIIDE_NUM_CHANNELS)
76: #define WDC_NPORTS 8 /* XXX */
77: #define WDC_NSHADOWREG 2 /* XXX */
78:
79: struct wdc_channel {
80: volatile u_int8_t *c_cmdbase;
81: volatile u_int8_t *c_ctlbase;
82: volatile u_int8_t *c_cmdreg[WDC_NPORTS + WDC_NSHADOWREG];
83: volatile u_int16_t *c_data;
84:
85: u_int8_t ndrives;
86: };
87:
88: #define WDC_READ_REG(chp, reg) *(chp)->c_cmdreg[(reg)]
89: #define WDC_WRITE_REG(chp, reg, val) *(chp)->c_cmdreg[(reg)] = (val)
90: #define WDC_READ_CTLREG(chp, reg) (chp)->c_ctlbase[(reg)]
91: #define WDC_WRITE_CTLREG(chp, reg, val) (chp)->c_ctlbase[(reg)] = (val)
92: #define WDC_READ_DATA(chp) *(chp)->c_data
93:
94: struct wd_softc {
95: #define WDF_LBA 0x0001
96: #define WDF_LBA48 0x0002
97: u_int16_t sc_flags;
98:
99: u_int sc_part;
100: u_int sc_unit;
101:
102: u_int64_t sc_capacity;
103:
104: struct ataparams sc_params;
105: struct disklabel sc_label;
106: struct wdc_channel sc_channel;
107: u_int sc_drive;
108: };
109:
110: struct wdc_command {
111: u_int8_t drive; /* drive id */
112:
113: u_int8_t r_command; /* Parameters to upload to registers */
114: u_int8_t r_head;
115: u_int16_t r_cyl;
116: u_int8_t r_sector;
117: u_int8_t r_count;
118: u_int8_t r_precomp;
119:
120: u_int16_t bcount;
121: void *data;
122:
123: u_int64_t r_blkno;
124: };
125:
126: int wdc_init (struct wd_softc*, u_int);
127: int wdccommand (struct wd_softc*, struct wdc_command*);
128: int wdccommandext (struct wd_softc*, struct wdc_command*);
129: int wdc_exec_read (struct wd_softc*, u_int8_t, daddr_t, void*);
130: int wdc_exec_identify (struct wd_softc*, void*);
131:
132: int pciide_init (struct wdc_channel*, u_int);
133:
134: #endif /* _STAND_WDVAR_H */
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