Annotation of sys/arch/arm/xscale/xscalereg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: xscalereg.h,v 1.2 2006/05/29 17:27:31 drahn Exp $ */
2: /* $NetBSD: xscalereg.h,v 1.2 2002/08/07 05:15:02 briggs Exp $ */
3:
4: /*
5: * Copyright (c) 2001 Wasabi Systems, Inc.
6: * All rights reserved.
7: *
8: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed for the NetBSD Project by
21: * Wasabi Systems, Inc.
22: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23: * or promote products derived from this software without specific prior
24: * written permission.
25: *
26: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36: * POSSIBILITY OF SUCH DAMAGE.
37: */
38:
39: #ifndef _ARM_XSCALE_XSCALEREG_H_
40: #define _ARM_XSCALE_XSCALEREG_H_
41:
42: /*
43: * Register definitions for the Intel XScale processor core.
44: */
45:
46: /*
47: * Performance Monitoring Unit (CP14)
48: *
49: * CP14.0 Performance Monitor Control Register
50: * CP14.1 Clock Counter
51: * CP14.2 Performance Counter Register 0
52: * CP14.3 Performance Counter Register 1
53: */
54:
55: #define PMNC_E 0x00000001 /* enable counters */
56: #define PMNC_P 0x00000002 /* reset both PMNs to 0 */
57: #define PMNC_C 0x00000004 /* clock counter reset */
58: #define PMNC_D 0x00000008 /* clock counter / 64 */
59: #define PMNC_PMN0_IE 0x00000010 /* enable PMN0 interrupt */
60: #define PMNC_PMN1_IE 0x00000020 /* enable PMN1 interrupt */
61: #define PMNC_CC_IE 0x00000040 /* enable clock counter interrupt */
62: #define PMNC_PMN0_IF 0x00000100 /* PMN0 overflow/interrupt */
63: #define PMNC_PMN1_IF 0x00000200 /* PMN1 overflow/interrupt */
64: #define PMNC_CC_IF 0x00000400 /* clock counter overflow/interrupt */
65: #define PMNC_EVCNT0_MASK 0x000ff000 /* event to count for PMN0 */
66: #define PMNC_EVCNT0_SHIFT 12
67: #define PMNC_EVCNT1_MASK 0x0ff00000 /* event to count for PMN1 */
68: #define PMNC_EVCNT1_SHIFT 20
69:
70: void xscale_pmu_init(void);
71:
72: #endif /* _ARM_XSCALE_XSCALEREG_H_ */
CVSweb