Annotation of sys/arch/arm/xscale/pxa2x0var.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: pxa2x0var.h,v 1.5 2005/05/27 21:10:05 uwe Exp $ */
2: /* $NetBSD: pxa2x0var.h,v 1.2 2003/06/05 13:48:28 scw Exp $ */
3:
4: /*
5: * Copyright (c) 2002 Genetec Corporation. All rights reserved.
6: * Written by Hiroyuki Bessho for Genetec Corporation.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed for the NetBSD Project by
19: * Genetec Corporation.
20: * 4. The name of Genetec Corporation may not be used to endorse or
21: * promote products derived from this software without specific prior
22: * written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
25: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
28: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34: * POSSIBILITY OF SUCH DAMAGE.
35: */
36:
37:
38: #ifndef _ARM_XSCALE_PXA2X0VAR_H_
39: #define _ARM_XSCALE_PXA2X0VAR_H_
40:
41: #include <arm/sa11x0/sa11x0_var.h>
42:
43: /* PXA2X0's integrated peripheral bus. */
44:
45: typedef int (* pxa2x0_irq_handler_t)(void *);
46:
47: struct pxaip_attach_args {
48: struct sa11x0_attach_args pxa_sa;
49: bus_dma_tag_t pxa_dmat;
50: int pxa_index; /* to specify device by index number */
51:
52: #define pxa_iot pxa_sa.sa_iot
53: #define pxa_addr pxa_sa.sa_addr
54: #define pxa_size pxa_sa.sa_size
55: #define pxa_intr pxa_sa.sa_intr
56: };
57:
58: #define cf_addr cf_loc[0]
59: #define cf_size cf_loc[1]
60: #define cf_intr cf_loc[2]
61: #define cf_index cf_loc[3]
62:
63:
64: extern struct bus_space pxa2x0_bs_tag;
65: extern struct arm32_bus_dma_tag pxa2x0_bus_dma_tag;
66: extern struct bus_space pxa2x0_a4x_bs_tag;
67:
68: /* misc. */
69: extern void pxa2x0_fcs_init(void);
70: extern void pxa2x0_freq_change(int);
71: extern void pxa2x0_turbo_mode(int);
72: extern int pxa2x0_i2c_master_tx( int, uint8_t *, int );
73:
74: /*
75: * Probe the memory controller to determine which SDRAM banks
76: * are populated, and what size SDRAM is present in each bank.
77: *
78: * This routine should be called from a port's initarm()
79: * function, with the first parameter set to the address
80: * of the memory controller's registers.
81: */
82: extern void pxa2x0_probe_sdram(vaddr_t, paddr_t *, psize_t *);
83:
84: /*
85: * Configure one or more clock enables in the Clock Manager's
86: * CKEN register.
87: */
88: extern void pxa2x0_clkman_config(u_int, int);
89:
90: /*
91: * Get/set the Real Time Clock's counter and alarm registers.
92: */
93: extern void pxa2x0_rtc_setalarm(u_int32_t);
94: extern u_int32_t pxa2x0_rtc_getalarm(void);
95: extern u_int32_t pxa2x0_rtc_getsecs(void);
96:
97: #endif /* _ARM_XSCALE_PXA2X0VAR_H_ */
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