Annotation of sys/arch/arm/xscale/pxa2x0reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: pxa2x0reg.h,v 1.30 2007/05/25 21:27:15 krw Exp $ */
2: /* $NetBSD: pxa2x0reg.h,v 1.4 2003/06/11 20:43:01 scw Exp $ */
3:
4: /*
5: * Copyright (c) 2002 Genetec Corporation. All rights reserved.
6: * Written by Hiroyuki Bessho for Genetec Corporation.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed for the NetBSD Project by
19: * Genetec Corporation.
20: * 4. The name of Genetec Corporation may not be used to endorse or
21: * promote products derived from this software without specific prior
22: * written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
25: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
28: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34: * POSSIBILITY OF SUCH DAMAGE.
35: */
36:
37:
38: /*
39: * Intel PXA2[15]0 processor is XScale based integrated CPU
40: *
41: * Reference:
42: * Intel(r) PXA250 and PXA210 Application Processors
43: * Developer's Manual
44: * (278522-001.pdf)
45: *
46: * Intel PXA 27x Processor Family Developers Manual (280000-002)
47: */
48: #ifndef _ARM_XSCALE_PXA2X0REG_H_
49: #define _ARM_XSCALE_PXA2X0REG_H_
50:
51: /* Borrow some register definitions from sa11x0 */
52: #include <arm/sa11x0/sa11x0_reg.h>
53:
54: #ifndef _LOCORE
55: #include <sys/types.h> /* for uint32_t */
56: #endif
57:
58: /*
59: * Chip select domains
60: */
61: #define PXA2X0_CS0_START 0x00000000
62: #define PXA2X0_CS1_START 0x04000000
63: #define PXA2X0_CS2_START 0x08000000
64: #define PXA2X0_CS3_START 0x0c000000
65: #define PXA2X0_CS4_START 0x10000000
66: #define PXA2X0_CS5_START 0x14000000
67:
68: #define PXA2X0_PCMCIA_SLOT0 0x20000000
69: #define PXA2X0_PCMCIA_SLOT1 0x30000000
70:
71: #define PXA2X0_PERIPH_START 0x40000000
72: /* #define PXA2X0_MEMCTL_START 0x48000000 */
73: #define PXA2X0_PERIPH_END 0x480fffff
74:
75: #define PXA2X0_SDRAM0_START 0xa0000000
76: #define PXA2X0_SDRAM1_START 0xa4000000
77: #define PXA2X0_SDRAM2_START 0xa8000000
78: #define PXA2X0_SDRAM3_START 0xac000000
79: #define PXA2X0_SDRAM_BANKS 4
80: #define PXA2X0_SDRAM_BANK_SIZE 0x04000000
81:
82: /*
83: * Physical address of integrated peripherals
84: */
85:
86: #define PXA2X0_DMAC_BASE 0x40000000
87: #define PXA2X0_DMAC_SIZE 0x300
88: #define PXA27X_DMAC_SIZE 0x0400
89: #define PXA2X0_FFUART_BASE 0x40100000 /* Full Function UART */
90: #define PXA2X0_BTUART_BASE 0x40200000 /* Bluetooth UART */
91: #define PXA2X0_I2C_BASE 0x40300000 /* I2C Bus Interface Unit */
92: #define PXA2X0_I2C_SIZE 0x16a4
93: #define PXA2X0_I2S_BASE 0x40400000 /* Inter-IC Sound Controller */
94: #define PXA2X0_I2S_SIZE 0x0084
95: #define PXA2X0_AC97_BASE 0x40500000 /* AC '97 Controller */
96: #define PXA2X0_AC97_SIZE 0x0600
97: #define PXA2X0_USBDC_BASE 0x40600000 /* USB Client Controller */
98: #define PXA2X0_USBDC_SIZE 0x0460
99: #define PXA2X0_STUART_BASE 0x40700000 /* Standard UART */
100: #define PXA2X0_ICP_BASE 0x40800000
101: #define PXA2X0_RTC_BASE 0x40900000
102: #define PXA2X0_RTC_SIZE 0x10
103: #define PXA2X0_OST_BASE 0x40a00000 /* OS Timer */
104: #define PXA2X0_OST_SIZE 0x24
105: #define PXA2X0_PWM0_BASE 0x40b00000
106: #define PXA2X0_PWM1_BASE 0x40c00000
107: #define PXA2X0_INTCTL_BASE 0x40d00000 /* Interrupt controller */
108: #define PXA2X0_INTCTL_SIZE 0x20
109: #define PXA2X0_GPIO_BASE 0x40e00000
110: #define PXA2X0_GPIO_SIZE 0x70
111: #define PXA2X0_POWMAN_BASE 0x40f00000 /* Power management */
112: #define PXA2X0_POWMAN_SIZE 0x1a4 /* incl. PI2C unit */
113: #define PXA2X0_SSP_BASE 0x41000000 /* SSP serial port */
114: #define PXA2X0_SSP1_BASE 0x41700000 /* PXA270 */
115: #define PXA2X0_SSP2_BASE 0x41900000 /* PXA270 */
116: #define PXA2X0_SSP_SIZE 0x40
117: #define PXA2X0_MMC_BASE 0x41100000 /* MultiMediaCard/SD/SDIO */
118: #define PXA2X0_MMC_SIZE 0x50
119: #define PXA2X0_CLKMAN_BASE 0x41300000 /* Clock Manager */
120: #define PXA2X0_CLKMAN_SIZE 12
121: #define PXA2X0_LCDC_BASE 0x44000000 /* LCD Controller */
122: #define PXA2X0_LCDC_SIZE 0x220
123: #define PXA2X0_MEMCTL_BASE 0x48000000 /* Memory Controller */
124: #define PXA2X0_MEMCTL_SIZE 0x84
125: #define PXA2X0_USBHC_BASE 0x4c000000 /* USB Host Controller */
126: #define PXA2X0_USBHC_SIZE 0x70
127:
128: /* width of interrupt controller */
129: #define ICU_LEN 32 /* but some are not used */
130: #define ICU_INT_HWMASK 0xffffff0f
131: #define PXA2X0_IRQ_MIN 1
132:
133: /*
134: * [0..1,15..16] are used as soft intrs by SI_TO_IRQBIT,
135: * and [4..6] are not likely to be used by us.
136: */
137: #define PXA2X0_INT_USBH2 2 /* USB host (all other events) */
138: #define PXA2X0_INT_USBH1 3 /* USB host (OHCI) */
139: #define PXA2X0_INT_OST 7 /* OS timers */
140: #define PXA2X0_INT_GPIO0 8
141: #define PXA2X0_INT_GPIO1 9
142: #define PXA2X0_INT_GPION 10 /* IRQ from GPIO[2..80] */
143: #define PXA2X0_INT_USB 11
144: #define PXA2X0_INT_PMU 12
145: #define PXA2X0_INT_I2S 13
146: #define PXA2X0_INT_AC97 14
147: #define PXA2X0_INT_LCD 17
148: #define PXA2X0_INT_I2C 18
149: #define PXA2X0_INT_ICP 19
150: #define PXA2X0_INT_STUART 20
151: #define PXA2X0_INT_BTUART 21
152: #define PXA2X0_INT_FFUART 22
153: #define PXA2X0_INT_MMC 23
154: #define PXA2X0_INT_SSP 24
155: #define PXA2X0_INT_DMA 25
156: #define PXA2X0_INT_OST0 26
157: #define PXA2X0_INT_OST1 27
158: #define PXA2X0_INT_OST2 28
159: #define PXA2X0_INT_OST3 29
160: #define PXA2X0_INT_RTCHZ 30
161: #define PXA2X0_INT_ALARM 31 /* RTC Alarm interrupt */
162:
163: /* Interrupt Controller similar to SA11x0's, but not exactly the same. */
164: #define INTCTL_ICIP 0x00
165: #define INTCTL_ICMR 0x04
166: #define INTCTL_ICLR 0x08
167: #define INTCTL_ICFP 0x0c
168: #define INTCTL_ICPR 0x10
169: #define INTCTL_ICCR 0x14
170: #define ICCR_DIM (1<<0)
171:
172: /* DMAC */
173: #define DMAC_N_CHANNELS 16
174: #define DMAC_N_CHANNELS_PXA27X 32
175: #define DMAC_N_PRIORITIES 3
176: #define DMAC_N_PRIORITIES_PXA27X 4
177:
178: #define DMAC_DCSR(n) ((n)*4)
179: #define DCSR_BUSERRINTR (1<<0) /* bus error interrupt */
180: #define DCSR_STARTINR (1<<1) /* start interrupt */
181: #define DCSR_ENDINTR (1<<2) /* end interrupt */
182: #define DCSR_STOPSTATE (1<<3) /* channel is not running */
183: #define DCSR_REQPEND (1<<8) /* request pending */
184: #define DCSR_STOPIRQEN (1<<29) /* stop interrupt enable */
185: #define DCSR_NODESCFETCH (1<<30) /* no-descriptor fetch mode */
186: #define DCSR_RUN (1<<31)
187: #define DMAC_DINT 0x00f0 /* DMA interrupt */
188: #define DMAC_DINT_MASK 0xffffu
189: #define DMAC_DRCMR(n) (0x100+(n)*4) /* Channel map register */
190: #define DRCMR_CHLNUM 0x0f /* channel number */
191: #define DRCMR_MAPVLD (1<<7) /* map valid */
192: #define DMAC_DDADR(n) (0x0200+(n)*16)
193: #define DDADR_STOP (1<<0)
194: #define DMAC_DSADR(n) (0x0204+(n)*16)
195: #define DMAC_DTADR(n) (0x0208+(n)*16)
196: #define DMAC_DCMD(n) (0x020c+(n)*16)
197: #define DCMD_LENGTH_MASK 0x1fff
198: #define DCMD_WIDTH_SHIFT 14
199: #define DCMD_WIDTH_0 (0<<DCMD_WIDTH_SHIFT) /* for mem-to-mem transfer*/
200: #define DCMD_WIDTH_1 (1<<DCMD_WIDTH_SHIFT)
201: #define DCMD_WIDTH_2 (2<<DCMD_WIDTH_SHIFT)
202: #define DCMD_WIDTH_4 (3<<DCMD_WIDTH_SHIFT)
203: #define DCMD_SIZE_SHIFT 16
204: #define DCMD_SIZE_8 (1<<DCMD_SIZE_SHIFT)
205: #define DCMD_SIZE_16 (2<<DCMD_SIZE_SHIFT)
206: #define DCMD_SIZE_32 (3<<DCMD_SIZE_SHIFT)
207: #define DCMD_LITTLE_ENDIAN (0<<18)
208: #define DCMD_ENDIRQEN (1<<21)
209: #define DCMD_STARTIRQEN (1<<22)
210: #define DCMD_FLOWTRG (1<<28) /* flow control by target */
211: #define DCMD_FLOWSRC (1<<29) /* flow control by source */
212: #define DCMD_INCTRGADDR (1<<30) /* increment target address */
213: #define DCMD_INCSRCADDR (1<<31) /* increment source address */
214:
215: #ifndef __ASSEMBLER__
216: /* DMA descriptor */
217: struct pxa2x0_dma_desc {
218: volatile uint32_t dd_ddadr;
219: #define DMAC_DESC_LAST 0x1
220: volatile uint32_t dd_dsadr;
221: volatile uint32_t dd_dtadr;
222: volatile uint32_t dd_dcmd; /* command and length */
223: };
224: #endif
225:
226: /* UART */
227: #define PXA2X0_COM_FREQ 14745600L
228:
229: /* I2C */
230: #define I2C_IBMR 0x1680 /* Bus monitor register */
231: #define I2C_IDBR 0x1688 /* Data buffer */
232: #define I2C_ICR 0x1690 /* Control register */
233: #define ICR_START (1<<0)
234: #define ICR_STOP (1<<1)
235: #define ICR_ACKNAK (1<<2)
236: #define ICR_TB (1<<3)
237: #define ICR_MA (1<<4)
238: #define ICR_SCLE (1<<5) /* PXA270? */
239: #define ICR_IUE (1<<6) /* PXA270? */
240: #define ICR_UR (1<<14) /* PXA270? */
241: #define ICR_FM (1<<15) /* PXA270? */
242: #define I2C_ISR 0x1698 /* Status register */
243: #define ISR_ACKNAK (1<<1)
244: #define ISR_ITE (1<<6)
245: #define ISR_IRF (1<<7)
246: #define I2C_ISAR 0x16a0 /* Slave address */
247:
248: /* Power Manager */
249: #define POWMAN_PMCR 0x00
250: #define POWMAN_PSSR 0x04 /* Sleep Status register */
251: #define PSSR_SSS (1<<0) /* Software Sleep Status */
252: #define PSSR_BFS (1<<1) /* Battery Fault Status */
253: #define PSSR_VFS (1<<2) /* VCC Fault Status */
254: #define PSSR_STS (1<<3) /* Standby Mode Status */
255: #define PSSR_PH (1<<4) /* Peripheral Control Hold */
256: #define PSSR_RDH (1<<5) /* Read Disable Hold */
257: #define PSSR_OTGPH (1<<6) /* OTG Peripheral Control Hold */
258: #define POWMAN_PSPR 0x08
259: #define POWMAN_PWER 0x0c
260: #define POWMAN_PRER 0x10
261: #define POWMAN_PFER 0x14
262: #define POWMAN_PEDR 0x18
263: #define POWMAN_PCFR 0x1c /* General Configuration register */
264: #define PCFR_OPDE (1<<0)
265: #define PCFR_GPR_EN (1<<4) /* PXA270 */
266: #define PCFR_PI2C_EN (1<<6) /* PXA270 */
267: #define PCFR_GP_ROD (1<<8) /* PXA270 */
268: #define PCFR_FVC (1<<10) /* PXA270 */
269: #define POWMAN_PGSR0 0x20 /* GPIO Sleep State register */
270: #define POWMAN_PGSR1 0x24
271: #define POWMAN_PGSR2 0x28
272: #define POWMAN_PGSR3 0x2c /* PXA270 */
273: #define POWMAN_RCSR 0x30 /* Reset Controller Status register */
274: #define RCSR_HWR (1<<0)
275: #define RCSR_WDR (1<<1)
276: #define RCSR_SMR (1<<2)
277: #define RCSR_GPR (1<<3)
278: #define POWMAN_PSLR 0x34 /* PXA270 */
279: #define POWMAN_PKWR 0x50 /* PXA270 */
280: #define POWMAN_PKSR 0x54 /* PXA270 */
281:
282: /* Power Manager I2C unit */
283: #define POWMAN_PIDBR 0x188
284: #define POWMAN_PICR 0x190
285: #define PICR_START ICR_START
286: #define PICR_STOP ICR_STOP
287: #define PICR_ACKNAK ICR_ACKNAK
288: #define PICR_TB ICR_TB
289: #define PICR_SCLE (1<<5) /* PXA270? */
290: #define PICR_IUE (1<<6) /* PXA270? */
291: #define PICR_UR (1<<14) /* PXA270? */
292: #define POWMAN_PISR 0x198
293: #define PISR_ACKNAK (1<<1)
294: #define PISR_ITE (1<<6)
295: #define PISR_IRF (1<<7)
296: #define POWMAN_PISAR 0x1a0
297:
298: /* Clock Manager */
299: #define CLKMAN_CCCR 0x00 /* Core Clock Configuration */
300: #define CCCR_CPDIS (1<<31) /* PXA270 */
301: #define CCCR_A (1<<25) /* PXA270 */
302: #define CCCR_TURBO_X1 (2<<7)
303: #define CCCR_TURBO_X15 (3<<7) /* x 1.5 */
304: #define CCCR_TURBO_X2 (4<<7)
305: #define CCCR_TURBO_X25 (5<<7) /* x 2.5 */
306: #define CCCR_TURBO_X3 (6<<7) /* x 3.0 */
307: /* PXA255 */
308: #define CCCR_RUN_X1 (1<<5)
309: #define CCCR_RUN_X2 (2<<5)
310: #define CCCR_RUN_X4 (3<<5)
311: #define CCCR_MEM_X27 (1<<0) /* x27, 99.53MHz */
312: #define CCCR_MEM_X32 (2<<0) /* x32, 117,96MHz */
313: #define CCCR_MEM_X36 (3<<0) /* x26, 132.71MHz */
314: #define CCCR_MEM_X40 (4<<0) /* x27, 99.53MHz */
315: #define CCCR_MEM_X45 (5<<0) /* x27, 99.53MHz */
316: #define CCCR_MEM_X9 (0x1f<<0) /* x9, 33.2MHz */
317: /* PXA27x: L is the core run frequency to 13MHz oscillator ratio. */
318: #define CCCR_RUN_X7 (7<<0) /* 91MHz, 91MHz mem, 91MHz LCD */
319: #define CCCR_RUN_X8 (8<<0) /* 104MHz, 104MHz mem, 52MHz LCD */
320: #define CCCR_RUN_X16 (16<<0) /* 208MHz, 104/208MHz mem, 104MHz LCD */
321:
322: #define CLKMAN_CKEN 0x04 /* Clock Enable Register */
323: #define CLKMAN_OSCC 0x08 /* Oscillator Configuration Register */
324:
325: #define CCCR_N_SHIFT 7
326: #define CCCR_N_MASK (0x07<<CCCR_N_SHIFT)
327: #define CCCR_M_SHIFT 5
328: #define CCCR_M_MASK (0x03<<CCCR_M_SHIFT)
329: #define CCCR_L_MASK 0x1f
330:
331: #define CKEN_PWM0 (1<<0)
332: #define CKEN_PWM1 (1<<1)
333: #define CKEN_AC97 (1<<2)
334: #define CKEN_SSP (1<<3)
335: #define CKEN_STUART (1<<5)
336: #define CKEN_FFUART (1<<6)
337: #define CKEN_BTUART (1<<7)
338: #define CKEN_I2S (1<<8)
339: #define CKEN_USBHC (1<<10)
340: #define CKEN_USBDC (1<<11)
341: #define CKEN_MMC (1<<12)
342: #define CKEN_FICP (1<<13)
343: #define CKEN_I2C (1<<14)
344: #define CKEN_PI2C (1<<15) /* PXA270? */
345: #define CKEN_LCD (1<<16)
346: #define CKEN_KEY (1<<19) /* PXA270? */
347: #define CKEN_MEM (1<<22) /* PXA270? */
348: #define CKEN_AC97CC (1<<31) /* PXA27x */
349:
350: #define OSCC_OOK (1<<0) /* 32.768KHz oscillator status */
351: #define OSCC_OON (1<<1) /* 32.768KHz oscillator */
352:
353: /*
354: * RTC
355: */
356: #define RTC_RCNR 0x0000 /* count register */
357: #define RTC_RTAR 0x0004 /* alarm register */
358: #define RTC_RTSR 0x0008 /* status register */
359: #define RTSR_AL (1<<0)
360: #define RTSR_HZ (1<<1)
361: #define RTSR_ALE (1<<2)
362: #define RTC_RTTR 0x000c /* trim register */
363: /*
364: * GPIO
365: */
366: #define GPIO_GPLR0 0x00 /* Level reg [31:0] */
367: #define GPIO_GPLR1 0x04 /* Level reg [63:32] */
368: #define GPIO_GPLR2 0x08 /* Level reg [80:64] PXA 270 [95:64] */
369:
370: #define GPIO_GPDR0 0x0c /* dir reg [31:0] */
371: #define GPIO_GPDR1 0x10 /* dir reg [63:32] */
372: #define GPIO_GPDR2 0x14 /* dir reg [80:64] PXA 270 [95:64] */
373:
374: #define GPIO_GPSR0 0x18 /* set reg [31:0] */
375: #define GPIO_GPSR1 0x1c /* set reg [63:32] */
376: #define GPIO_GPSR2 0x20 /* set reg [80:64] PXA 270 [95:64] */
377:
378: #define GPIO_GPCR0 0x24 /* clear reg [31:0] */
379: #define GPIO_GPCR1 0x28 /* clear reg [63:32] */
380: #define GPIO_GPCR2 0x2c /* clear reg [80:64] PXA 270 [95:64] */
381:
382: #define GPIO_GPER0 0x30 /* rising edge [31:0] */
383: #define GPIO_GPER1 0x34 /* rising edge [63:32] */
384: #define GPIO_GPER2 0x38 /* rising edge [80:64] PXA 270 [95:64] */
385:
386: #define GPIO_GRER0 0x30 /* rising edge [31:0] */
387: #define GPIO_GRER1 0x34 /* rising edge [63:32] */
388: #define GPIO_GRER2 0x38 /* rising edge [80:64] PXA 270 [95:64] */
389:
390: #define GPIO_GFER0 0x3c /* falling edge [31:0] */
391: #define GPIO_GFER1 0x40 /* falling edge [63:32] */
392: #define GPIO_GFER2 0x44 /* falling edge [80:64] PXA 270 [95:64] */
393:
394: #define GPIO_GEDR0 0x48 /* edge detect [31:0] */
395: #define GPIO_GEDR1 0x4c /* edge detect [63:32] */
396: #define GPIO_GEDR2 0x50 /* edge detect [80:64] PXA 270 [95:64] */
397:
398: #define GPIO_GAFR0_L 0x54 /* alternate function [15:0] */
399: #define GPIO_GAFR0_U 0x58 /* alternate function [31:16] */
400: #define GPIO_GAFR1_L 0x5c /* alternate function [47:32] */
401: #define GPIO_GAFR1_U 0x60 /* alternate function [63:48] */
402: #define GPIO_GAFR2_L 0x64 /* alternate function [79:64] */
403: #define GPIO_GAFR2_U 0x68 /* alternate function [80] PXA 270 [95:80] */
404:
405: #define GPIO_GAFR3_L 0x6C /* alternate function PXA 270 [111:96] */
406: #define GPIO_GAFR3_U 0x70 /* alternate function PXA 270 [120:112] */
407:
408: #define GPIO_GPLR3 0x100 /* Level PXA 270 [120:96] */
409: #define GPIO_GPDR3 0x10C /* dir reg PXA 270 [120:96] */
410: #define GPIO_GPSR3 0x118 /* set reg PXA 270 [120:96] */
411: #define GPIO_GPCR3 0x124 /* clear reg PXA 270 [120:96] */
412: #define GPIO_GRER3 0x130 /* rising edge PXA 270 [120:96] */
413: #define GPIO_GFER3 0x13c /* falling edge PXA 270 [120:96] */
414: #define GPIO_GEDR3 0x148 /* edge detect PXA270 [120:96] */
415:
416: #define GPIO_REG(r, pin) ((r) + \
417: ((pin > 95) ? GPIO_GPLR3 : (((pin) / 32) * 4)))
418: #define GPIO_BANK(pin) ((pin) / 32)
419: #define GPIO_BIT(pin) (1u << ((pin) & 0x1f))
420: #define GPIO_FN_REG(pin) (GPIO_GAFR0_L + (((pin) / 16) * 4))
421: #define GPIO_FN_SHIFT(pin) ((pin & 0xf) * 2)
422:
423: #define GPIO_IN 0x00 /* Regular GPIO input pin */
424: #define GPIO_OUT 0x10 /* Regular GPIO output pin */
425: #define GPIO_ALT_FN_1_IN 0x01 /* Alternate function 1 input */
426: #define GPIO_ALT_FN_1_OUT 0x11 /* Alternate function 1 output */
427: #define GPIO_ALT_FN_2_IN 0x02 /* Alternate function 2 input */
428: #define GPIO_ALT_FN_2_OUT 0x12 /* Alternate function 2 output */
429: #define GPIO_ALT_FN_3_IN 0x03 /* Alternate function 3 input */
430: #define GPIO_ALT_FN_3_OUT 0x13 /* Alternate function 3 output */
431: #define GPIO_SET 0x20 /* Initial state is Set */
432: #define GPIO_CLR 0x00 /* Initial state is Clear */
433:
434: #define GPIO_FN_MASK 0x03
435: #define GPIO_FN_IS_OUT(n) ((n) & GPIO_OUT)
436: #define GPIO_FN_IS_SET(n) ((n) & GPIO_SET)
437: #define GPIO_FN(n) ((n) & GPIO_FN_MASK)
438: #define GPIO_IS_GPIO(n) (GPIO_FN(n) == 0)
439: #define GPIO_IS_GPIO_IN(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_IN)
440: #define GPIO_IS_GPIO_OUT(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_OUT)
441:
442: #define GPIO_NPINS_25x 85
443: #define GPIO_NPINS 121
444:
445: /*
446: * memory controller
447: */
448:
449: #define MEMCTL_MDCNFG 0x0000
450: #define MDCNFG_DE0 (1<<0)
451: #define MDCNFG_DE1 (1<<1)
452: #define MDCNFD_DWID01_SHIFT 2
453: #define MDCNFD_DCAC01_SHIFT 3
454: #define MDCNFD_DRAC01_SHIFT 5
455: #define MDCNFD_DNB01_SHIFT 7
456: #define MDCNFG_DE2 (1<<16)
457: #define MDCNFG_DE3 (1<<17)
458: #define MDCNFD_DWID23_SHIFT 18
459: #define MDCNFD_DCAC23_SHIFT 19
460: #define MDCNFD_DRAC23_SHIFT 21
461: #define MDCNFD_DNB23_SHIFT 23
462:
463: #define MDCNFD_DWID_MASK 0x1
464: #define MDCNFD_DCAC_MASK 0x3
465: #define MDCNFD_DRAC_MASK 0x3
466: #define MDCNFD_DNB_MASK 0x1
467:
468: #define MEMCTL_MDREFR 0x04 /* refresh control register */
469: #define MDREFR_DRI 0xfff
470: #define MDREFR_E0PIN (1<<12)
471: #define MDREFR_K0RUN (1<<13) /* SDCLK0 enable */
472: #define MDREFR_K0DB2 (1<<14) /* SDCLK0 1/2 freq */
473: #define MDREFR_E1PIN (1<<15)
474: #define MDREFR_K1RUN (1<<16) /* SDCLK1 enable */
475: #define MDREFR_K1DB2 (1<<17) /* SDCLK1 1/2 freq */
476: #define MDREFR_K2RUN (1<<18) /* SDCLK2 enable */
477: #define MDREFR_K2DB2 (1<<19) /* SDCLK2 1/2 freq */
478: #define MDREFR_APD (1<<20) /* Auto Power Down */
479: #define MDREFR_SLFRSH (1<<22) /* Self Refresh */
480: #define MDREFR_K0FREE (1<<23) /* SDCLK0 free run */
481: #define MDREFR_K1FREE (1<<24) /* SDCLK1 free run */
482: #define MDREFR_K2FREE (1<<25) /* SDCLK2 free run */
483:
484: #define MEMCTL_MSC0 0x08 /* Asynchronous Static memory Control CS[01] */
485: #define MEMCTL_MSC1 0x0c /* Asynchronous Static memory Control CS[23] */
486: #define MEMCTL_MSC2 0x10 /* Asynchronous Static memory Control CS[45] */
487: #define MSC_RBUFF_SHIFT 15 /* return data buffer */
488: #define MSC_RBUFF (1<<MSC_RBUFF_SHIFT)
489: #define MSC_RRR_SHIFT 12 /* recovery time */
490: #define MSC_RRR (7<<MSC_RRR_SHIFT)
491: #define MSC_RDN_SHIFT 8 /* ROM delay next access */
492: #define MSC_RDN (0x0f<<MSC_RDN_SHIFT)
493: #define MSC_RDF_SHIFT 4 /* ROM delay first access*/
494: #define MSC_RDF (0x0f<<MSC_RDF_SHIFT)
495: #define MSC_RBW_SHIFT 3 /* 32/16 bit bus */
496: #define MSC_RBW (1<<MSC_RBW_SHIFT)
497: #define MSC_RT_SHIFT 0 /* type */
498: #define MSC_RT (7<<MSC_RT_SHIFT)
499: #define MSC_RT_NONBURST 0
500: #define MSC_RT_SRAM 1
501: #define MSC_RT_BURST4 2
502: #define MSC_RT_BURST8 3
503: #define MSC_RT_VLIO 4
504:
505: /* expansion memory timing configuration */
506: #define MEMCTL_MCMEM(n) (0x28+4*(n))
507: #define MEMCTL_MCATT(n) (0x30+4*(n))
508: #define MEMCTL_MCIO(n) (0x38+4*(n))
509:
510: #define MC_HOLD_SHIFT 14
511: #define MC_ASST_SHIFT 7
512: #define MC_SET_SHIFT 0
513: #define MC_TIMING_VAL(hold,asst,set) (((hold)<<MC_HOLD_SHIFT)| \
514: ((asst)<<MC_ASST_SHIFT)|((set)<<MC_SET_SHIFT))
515:
516: #define MEMCTL_MECR 0x14 /* Expansion memory configuration */
517: #define MECR_NOS (1<<0) /* Number of sockets */
518: #define MECR_CIT (1<<1) /* Card-is-there */
519:
520: #define MEMCTL_MDMRS 0x0040
521:
522: #define MEMCTL_ARB_CNTRL 0x0048 /* System Bus Arbiter */
523:
524: /*
525: * LCD Controller
526: */
527: #define LCDC_LCCR0 0x000 /* Controller Control Register 0 */
528: #define LCCR0_ENB (1U<<0) /* LCD Controller Enable */
529: #define LCCR0_CMS (1U<<1) /* Color/Mono select */
530: #define LCCR0_SDS (1U<<2) /* Single/Dual -panel */
531: #define LCCR0_LDM (1U<<3) /* LCD Disable Done Mask */
532: #define LCCR0_SFM (1U<<4) /* Start of Frame Mask */
533: #define LCCR0_IUM (1U<<5) /* Input FIFO Underrun Mask */
534: #define LCCR0_EFM (1U<<6) /* End of Frame Mask */
535: #define LCCR0_PAS (1U<<7) /* Passive/Active Display select */
536: #define LCCR0_DPD (1U<<9) /* Double-Pixel Data pin mode */
537: #define LCCR0_DIS (1U<<10) /* LCD Disable */
538: #define LCCR0_QDM (1U<<11) /* LCD Quick Disable Mask */
539: #define LCCR0_BM (1U<<20) /* Branch Mask */
540: #define LCCR0_OUM (1U<<21) /* Output FIFO Underrun Mask */
541: /* PXA270 */
542: #define LCCR0_LCDT (1U<<22) /* LCD Panel Type */
543: #define LCCR0_RDSTM (1U<<23) /* Read Status Interrupt Mask */
544: #define LCCR0_CMDIM (1U<<24) /* Command Interrupt Mask */
545: #define LCCR0_OUC (1U<<25) /* Overlay Underlay Control */
546: #define LCCR0_LDDALT (1U<<26) /* LDD Alternate Mapping Control Bit */
547:
548: #define LCCR0_IMASK (LCCR0_LDM|LCCR0_SFM|LCCR0_IUM|LCCR0_EFM|LCCR0_QDM|LCCR0_BM|LCCR0_OUM)
549:
550:
551: #define LCDC_LCCR1 0x004 /* Controller Control Register 1 */
552: #define LCDC_LCCR2 0x008 /* Controller Control Register 2 */
553: #define LCDC_LCCR3 0x00c /* Controller Control Register 2 */
554: #define LCCR3_BPP_SHIFT 24 /* Bits per pixel */
555: #define LCCR3_BPP (0x07<<LCCR3_BPP_SHIFT)
556: #define LCDC_FBR0 0x020 /* DMA ch0 frame branch register */
557: #define LCDC_FBR1 0x024 /* DMA ch1 frame branch register */
558: #define LCDC_LCSR 0x038 /* controller status register */
559: #define LCSR_LDD (1U<<0) /* LCD disable done */
560: #define LCSR_SOF (1U<<1) /* Start of frame */
561: #define LCDC_LIIDR 0x03c /* controller interrupt ID Register */
562: #define LCDC_TRGBR 0x040 /* TMED RGB Speed Register */
563: #define LCDC_TCR 0x044 /* TMED Control Register */
564: #define LCDC_FDADR0 0x200 /* DMA ch0 frame descriptor address */
565: #define LCDC_FSADR0 0x204 /* DMA ch0 frame source address */
566: #define LCDC_FIDR0 0x208 /* DMA ch0 frame ID register */
567: #define LCDC_LDCMD0 0x20c /* DMA ch0 command register */
568: #define LCDC_FDADR1 0x210 /* DMA ch1 frame descriptor address */
569: #define LCDC_FSADR1 0x214 /* DMA ch1 frame source address */
570: #define LCDC_FIDR1 0x218 /* DMA ch1 frame ID register */
571: #define LCDC_LDCMD1 0x21c /* DMA ch1 command register */
572:
573: /*
574: * MMC/SD controller
575: */
576: #define MMC_STRPCL 0x00 /* start/stop MMC clock */
577: #define STRPCL_NOOP 0
578: #define STRPCL_STOP 1 /* stop MMC clock */
579: #define STRPCL_START 2 /* start MMC clock */
580: #define MMC_STAT 0x04 /* status register */
581: #define STAT_READ_TIME_OUT (1<<0)
582: #define STAT_TIMEOUT_RESPONSE (1<<1)
583: #define STAT_CRC_WRITE_ERROR (1<<2)
584: #define STAT_CRC_READ_ERROR (1<<3)
585: #define STAT_SPI_READ_ERROR_TOKEN (1<<4)
586: #define STAT_RES_CRC_ERR (1<<5)
587: #define STAT_XMIT_FIFO_EMPTY (1<<6) /* (PXA27x: reserved) */
588: #define STAT_RECV_FIFO_FULL (1<<7) /* (PXA27x: reserved) */
589: #define STAT_CLK_EN (1<<8)
590: #define STAT_DATA_TRAN_DONE (1<<11)
591: #define STAT_PRG_DONE (1<<12)
592: #define STAT_END_CMD_RES (1<<13)
593: #define MMC_CLKRT 0x08 /* MMC clock rate */
594: #define CLKRT_20M 0
595: #define CLKRT_10M 1
596: #define CLKRT_5M 2
597: #define CLKRT_2_5M 3
598: #define CLKRT_1_25M 4
599: #define CLKRT_625K 5
600: #define CLKRT_312K 6
601: #define MMC_SPI 0x0c /* SPI mode control */
602: #define SPI_EN (1<<0) /* enable SPI mode */
603: #define SPI_CRC_ON (1<<1) /* enable CRC generation */
604: #define SPI_CS_EN (1<<2) /* Enable CS[01] */
605: #define SPI_CS_ADDRESS (1<<3) /* CS0/CS1 */
606: #define MMC_CMDAT 0x10 /* command/response/data */
607: #define CMDAT_RESPONSE_FORMAT 0x03
608: #define CMDAT_RESPONSE_FORMAT_NO 0 /* no response */
609: #define CMDAT_RESPONSE_FORMAT_R1 1 /* R1, R1b, R4, R5, R5b, R6 */
610: #define CMDAT_RESPONSE_FORMAT_R2 2
611: #define CMDAT_RESPONSE_FORMAT_R3 3
612: #define CMDAT_DATA_EN (1<<2)
613: #define CMDAT_WRITE (1<<3) /* 1=write 0=read operation */
614: #define CMDAT_STREAM_BLOCK (1<<4) /* stream mode */
615: #define CMDAT_BUSY (1<<5) /* busy signal is expected */
616: #define CMDAT_INIT (1<<6) /* precede command with 80 clocks */
617: #define CMDAT_MMC_DMA_EN (1<<7) /* DMA enable */
618: #define MMC_RESTO 0x14 /* expected response time out */
619: #define MMC_RDTO 0x18 /* expected data read time out */
620: #define MMC_BLKLEN 0x1c /* block length of data transaction */
621: #define MMC_NUMBLK 0x20 /* number of blocks (block mode) */
622: #define MMC_PRTBUF 0x24 /* partial MMC_TXFIFO written */
623: #define PRTBUF_BUF_PART_FULL (1<<0) /* buffer partially full */
624: #define MMC_I_MASK 0x28 /* interrupt mask */
625: #define MMC_I_REG 0x2c /* interrupt register */
626: #define MMC_I_DATA_TRAN_DONE (1<<0)
627: #define MMC_I_PRG_DONE (1<<1)
628: #define MMC_I_END_CMD_RES (1<<2)
629: #define MMC_I_STOP_CMD (1<<3)
630: #define MMC_I_CLK_IS_OFF (1<<4)
631: #define MMC_I_RXFIFO_RD_REQ (1<<5)
632: #define MMC_I_TXFIFO_WR_REQ (1<<6)
633: #define MMC_I_DAT_ERR (1<<8) /* PXA27x */
634: #define MMC_I_RES_ERR (1<<9) /* PXA27x */
635: #define MMC_I_SDIO_INT (1<<11) /* PXA27x */
636: #define MMC_CMD 0x30 /* index of current command */
637: #define MMC_ARGH 0x34 /* MSW part of the current command arg */
638: #define MMC_ARGL 0x38 /* LSW part of the current command arg */
639: #define MMC_RES 0x3c /* response FIFO */
640: #define MMC_RXFIFO 0x40 /* receive FIFO */
641: #define MMC_TXFIFO 0x44 /* transmit FIFO */
642:
643:
644: /*
645: * Inter-IC Sound (I2S) Controller
646: */
647: #define I2S_SACR0 0x0000 /* Serial Audio Global Control */
648: #define SACR0_ENB (1<<0) /* Enable I2S Function */
649: #define SACR0_BCKD (1<<2) /* I/O Direction of I2S_BITCLK */
650: #define SACR0_RST (1<<3) /* FIFO Reset */
651: #define SACR0_EFWR (1<<4) /* Special-Purpose FIFO W/R Func */
652: #define SACR0_STRF (1<<5) /* Select TX or RX FIFO */
653: #define SACR0_TFTH_MASK (0xf<<8) /* Trans FIFO Intr/DMA Trig Thresh */
654: #define SACR0_RFTH_MASK (0xf<<12) /* Recv FIFO Intr/DMA Trig Thresh */
655: #define SACR0_SET_TFTH(x) (((x) & 0xf)<<8)
656: #define SACR0_SET_RFTH(x) (((x) & 0xf)<<12)
657: #define I2S_SACR1 0x0004 /* Serial Audio I2S/MSB-Justified Control */
658: #define SACR1_AMSL (1<<0) /* Specify Alt Mode (I2S or MSB) */
659: #define SACR1_DREC (1<<3) /* Disable Recording Func */
660: #define SACR1_DRPL (1<<4) /* Disable Replay Func */
661: #define SACR1_ENLBF (1<<5) /* Enable Interface Loopback Func */
662: #define I2S_SASR0 0x000c /* Serial Audio I2S/MSB-Justified Status */
663: #define SASR0_TNF (1<<0) /* Transmit FIFO Not Full */
664: #define SASR0_RNE (1<<1) /* Recv FIFO Not Empty */
665: #define SASR0_BSY (1<<2) /* I2S Busy */
666: #define SASR0_TFS (1<<3) /* Trans FIFO Service Request */
667: #define SASR0_RFS (1<<4) /* Recv FIFO Service Request */
668: #define SASR0_TUR (1<<5) /* Trans FIFO Underrun */
669: #define SASR0_ROR (1<<6) /* Recv FIFO Overrun */
670: #define SASR0_I2SOFF (1<<7) /* I2S Controller Off */
671: #define SASR0_TFL_MASK (0xf<<8) /* Trans FIFO Level */
672: #define SASR0_RFL_MASK (0xf<<12) /* Recv FIFO Level */
673: #define SASR0_GET_TFL(x) (((x) & 0xf) >> 8)
674: #define SASR0_GET_RFL(x) (((x) & 0xf) >> 12)
675: #define I2S_SAIMR 0x0014 /* Serial Audio Interrupt Mask */
676: #define SAIMR_TFS (1<<3) /* Enable TX FIFO Service Req Intr */
677: #define SAIMR_RFS (1<<4) /* Enable RX FIFO Service Req Intr */
678: #define SAIMR_TUR (1<<5) /* Enable TX FIFO Underrun Intr */
679: #define SAIMR_ROR (1<<6) /* Enable RX FIFO Overrun Intr */
680: #define I2S_SAICR 0x0018 /* Serial Audio Interrupt Clear */
681: #define SAICR_TUR (1<<5) /* Clear Intr and SASR0_TUR */
682: #define SAICR_ROR (1<<6) /* Clear Intr and SASR0_ROR */
683: #define I2S_SADIV 0x0060 /* Audio Clock Divider */
684: #define SADIV_MASK 0x7f
685: #define SADIV_3_058MHz 0x0c /* 3.058 MHz */
686: #define SADIV_2_836MHz 0x0d /* 2.836 MHz */
687: #define SADIV_1_405MHz 0x1a /* 1.405 MHz */
688: #define SADIV_1_026MHz 0x24 /* 1.026 MHz */
689: #define SADIV_702_75kHz 0x34 /* 702.75 kHz */
690: #define SADIV_513_25kHz 0x48 /* 513.25 kHz */
691: #define I2S_SADR 0x0080 /* Serial Audio Data Register */
692: #define SADR_DTL (0xffff<<0) /* Left Data Sample */
693: #define SADR_DTH (0xffff<<16) /* Right Data Sample */
694:
695: /*
696: * AC '97 Controller
697: */
698: #define AC97_POCR 0x0000 /* PCM Out Control Register */
699: #define POCR_FSRIE (1<<1) /* FIFO Service Request Intr Enable */
700: #define POCR_FEIE (1<<3) /* FIFO Error Intr Enable */
701: #define AC97_PCMICR 0x0004 /* PCM In Control Register */
702: #define PCMICR_FSRIE (1<<1) /* FIFO Service Request Intr Enable */
703: #define PCMICR_FEIE (1<<3) /* FIFO Error Intr Enable */
704: #define AC97_MCCR 0x0008 /* Microphone In Control Register */
705: #define MCCR_FSRIE (1<<1) /* FIFO Service Request Intr Enable */
706: #define MCCR_FEIE (1<<3) /* FIFO Error Intr Enable */
707: #define AC97_GCR 0x000c /* Global Control Register */
708: #define GCR_GPI_IE (1<<0) /* Codec GPI Interrupt Enable */
709: #define GCR_nCRST (1<<1) /* AC '97 Cold Reset */
710: #define GCR_WRST (1<<2) /* AC '97 Warm Reset */
711: #define GCR_ACOFF (1<<3) /* AC-Link Shut Off */
712: #define GCR_PRES_IE (1<<4) /* Primary Resume Intr Enable */
713: #define GCR_SRES_IE (1<<5) /* Secondary Resume Intr Enable */
714: #define GCR_PRDY_IE (1<<8) /* Primary Ready Intr Enable */
715: #define GCR_SRDY_IE (1<<9) /* Secondary Ready Intr Enable */
716: #define GCR_SDONE_IE (1<<18) /* Status Done Intr Enable */
717: #define GCR_CDONE_IE (1<<19) /* Command Done Intr Enable */
718: #define GCR_nDMAEN (1<<24) /* DMA Enable (PXA27x) */
719: #define AC97_POSR 0x0010 /* PCM Out Status Register */
720: #define POSR_FSR (1<<2) /* FIFO Service Request */
721: #define POSR_FIFOE (1<<4) /* FIFO Error */
722: #define AC97_PCMISR 0x0014 /* PCM In Status Register */
723: #define PCMISR_FSR (1<<2) /* FIFO Service Request */
724: #define PCMISR_ECC (1<<3) /* DMA End of Chain Intr */
725: #define PCMISR_FIFOE (1<<4) /* FIFO Error */
726: #define AC97_MCSR 0x0018 /* Microphone In Status Register */
727: #define MCSR_FSR (1<<2) /* FIFO Service Request */
728: #define MCSR_ECC (1<<3) /* DMA End of Chain Intr */
729: #define MCSR_FIFOE (1<<4) /* FIFO Error */
730: #define AC97_GSR 0x001c /* Global Status Register */
731: #define GSR_GSCI (1<<0) /* Codec GPI Status Change Intr */
732: #define GSR_MIINT (1<<1) /* Modem-In Intr */
733: #define GSR_MOINT (1<<2) /* Modem-Out Intr */
734: #define GSR_ACOFFD (1<<3) /* AC-link Shut Off Done */
735: #define GSR_PIINT (1<<5) /* PCM-In Intr */
736: #define GSR_POINT (1<<6) /* PCM-Out Intr */
737: #define GSR_MCINT (1<<7) /* Mic-In Intr */
738: #define GSR_PCRDY (1<<8) /* Primay Codec Ready */
739: #define GSR_SCRDY (1<<9) /* Secondary Codec Ready */
740: #define GSR_PRESINT (1<<10) /* Primary Resume Intr */
741: #define GSR_SRESINT (1<<11) /* Secondary Resume Intr */
742: #define GSR_B1S12 (1<<12) /* Bit 1 of Slot 12 */
743: #define GSR_B2S12 (1<<13) /* Bit 2 of Slot 12 */
744: #define GSR_B3S12 (1<<14) /* Bit 3 of Slot 12 */
745: #define GSR_RCS (1<<15) /* Read Completion Status */
746: #define GSR_SDONE (1<<18) /* Status Done */
747: #define GSR_CDONE (1<<19) /* Command Done */
748: #define AC97_CAR 0x0020 /* Codec Access Register */
749: #define CAR_CAIP (1<<0) /* Codec Access In Progress */
750: /* 0x0024 to 0x003c is reserved */
751: #define AC97_PCDR 0x0040 /* PCM Data Register */
752: #define PCDR_PCML (0xffff<<0) /* PCM Left Channel Data */
753: #define PCDR_PCMR (0xffff<<16) /* PCM Right Channel Data */
754: /* 0x0044 to 0x005c is reserved */
755: #define AC97_MCDR 0x0060 /* Microphone In Data Register */
756: #define MCDR_MCDAT (0xffff<<0) /* Mic-In Data */
757: /* 0x0064 to 0x00fc is reserved */
758: #define AC97_MOCR 0x0100 /* Modem Out Control Register */
759: #define MOCR_FSRIE (1<<1) /* FIFO Service Request Intr Enable */
760: #define MOCR_FEIE (1<<3) /* FIFO Error Intr Enable */
761: /* 0x0104 is reserved */
762: #define AC97_MICR 0x0108 /* Modem In Control Register */
763: #define MICR_FSRIE (1<<1) /* FIFO Service Request Intr Enable */
764: #define MICR_FEIE (1<<3) /* FIFO Error Intr Enable */
765: /* 0x010c is reserved */
766: #define AC97_MOSR 0x0110 /* Modem Out Status Register */
767: #define MOSR_FSR (1<<2) /* FIFO Service Request */
768: #define MOSR_FIFOE (1<<2) /* FIFO Error */
769: /* 0x0114 is reserved */
770: #define AC97_MISR 0x0118 /* Modem In Status Register */
771: #define MOSR_FSR (1<<2) /* FIFO Service Request */
772: #define MOSR_EOC (1<<2) /* DMA End of Chain Intr */
773: #define MOSR_FIFOE (1<<2) /* FIFO Error */
774: /* 0x011c to 0x013c is reserved */
775: #define AC97_MODR 0x0140 /* Modem Data Register */
776: #define MODR_MODAT (0xffff<<0) /* Modem Data */
777: /* 0x0144 to 0x01fc is reserved */
778:
779: #define AC97_PRIAUDIO 0x0200 /* Primary Audio Codec Registers */
780: #define AC97_SECAUDIO 0x0300 /* Secondary Audio Codec Registers */
781: #define AC97_PRIMODEM 0x0400 /* Primary Modem Codec Registers */
782: #define AC97_SECMODEM 0x0500 /* Secondary modem Codec Registers */
783:
784: /*
785: * USB device controller differs between pxa255 and pxa27x, defined separately
786: */
787:
788: /*
789: * USB Host Controller
790: */
791: #define USBHC_STAT 0x0060 /* UHC Status Register */
792: #define USBHC_STAT_RWUE (1<<7) /* HCI Remote Wake-Up Event */
793: #define USBHC_STAT_HBA (1<<8) /* HCI Buffer Active */
794: #define USBHC_STAT_HTA (1<<10) /* HCI Transfer Abort */
795: #define USBHC_STAT_UPS1 (1<<11) /* USB Power Sense Port 1 */
796: #define USBHC_STAT_UPS2 (1<<12) /* USB Power Sense Port 2 */
797: #define USBHC_STAT_UPRI (1<<13) /* USB Port Resume Interrupt */
798: #define USBHC_STAT_SBTAI (1<<14) /* System Bus Target Abort Interrupt */
799: #define USBHC_STAT_SBMAI (1<<15) /* System Bus Master Abort Interrupt */
800: #define USBHC_STAT_UPS3 (1<<16) /* USB Power Sense Port 3 */
801: #define USBHC_STAT_MASK (USBHC_STAT_RWUE | USBHC_STAT_HBA | \
802: USBHC_STAT_HTA | USBHC_STAT_UPS1 | USBHC_STAT_UPS2 | USBHC_STAT_UPRI | \
803: USBHC_STAT_SBTAI | USBHC_STAT_SBMAI | USBHC_STAT_UPS3)
804: #define USBHC_HR 0x0064 /* UHC Reset Register */
805: #define USBHC_HR_FSBIR (1<<0) /* Force System Bus Interface Reset */
806: #define USBHC_HR_FHR (1<<1) /* Force Host Controller Reset */
807: #define USBHC_HR_CGR (1<<2) /* Clock Generation Reset */
808: #define USBHC_HR_SSDC (1<<3) /* Simulation Scale Down Clock */
809: #define USBHC_HR_UIT (1<<4) /* USB Interrupt Test */
810: #define USBHC_HR_SSE (1<<5) /* Sleep Standby Enable */
811: #define USBHC_HR_PSPL (1<<6) /* Power Sense Polarity Low */
812: #define USBHC_HR_PCPL (1<<7) /* Power Control Polarity Low */
813: #define USBHC_HR_SSEP1 (1<<9) /* Sleep Standby Enable for Port 1 */
814: #define USBHC_HR_SSEP2 (1<<10) /* Sleep Standby Enable for Port 2 */
815: #define USBHC_HR_SSEP3 (1<<11) /* Sleep Standby Enable for Port 3 */
816: #define USBHC_HR_MASK (USBHC_HR_FSBIR | USBHC_HR_FHR | \
817: USBHC_HR_CGR | USBHC_HR_SSDC | USBHC_HR_UIT | USBHC_HR_SSE | \
818: USBHC_HR_PSPL | USBHC_HR_PCPL | USBHC_HR_SSEP1 | USBHC_HR_SSEP2 | \
819: USBHC_HR_SSEP3)
820: #define USBHC_HIE 0x0068 /* UHC Interrupt Enable Register */
821: #define USBHC_HIE_RWIE (1<<7) /* HCI Remote Wake-Up */
822: #define USBHC_HIE_HBAIE (1<<8) /* HCI Buffer Active */
823: #define USBHC_HIE_TAIE (1<<10) /* HCI Interface Transfer Abort */
824: #define USBHC_HIE_UPS1IE (1<<11) /* USB Power Sense Port 1 */
825: #define USBHC_HIE_UPS2IE (1<<12) /* USB Power Sense Port 2 */
826: #define USBHC_HIE_UPRIE (1<<13) /* USB Port Resume */
827: #define USBHC_HIE_UPS3IE (1<<14) /* USB Power Sense Port 3 */
828: #define USBHC_HIE_MASK (USBHC_HIE_RWIE | USBHC_HIE_HBAIE | \
829: USBHC_HIE_TAIE | USBHC_HIE_UPS1IE | USBHC_HIE_UPS2IE | USBHC_HIE_UPRIE | \
830: USBHC_HIE_UPS3IE)
831: #define USBHC_HIT 0x006C /* UHC Interrupt Test Register */
832: #define USBHC_HIT_RWUT (1<<7) /* HCI Remote Wake-Up */
833: #define USBHC_HIT_BAT (1<<8) /* HCI Buffer Active */
834: #define USBHC_HIT_IRQT (1<<9) /* Normal OHC */
835: #define USBHC_HIT_TAT (1<<10) /* HCI Interface Transfer Abort */
836: #define USBHC_HIT_UPS1T (1<<11) /* USB Power Sense Port 1 */
837: #define USBHC_HIT_UPS2T (1<<12) /* USB Power Sense Port 2 */
838: #define USBHC_HIT_UPRT (1<<13) /* USB Port Resume */
839: #define USBHC_HIT_STAT (1<<14) /* System Bus Target Abort */
840: #define USBHC_HIT_SMAT (1<<15) /* System Bus Master Abort */
841: #define USBHC_HIT_UPS3T (1<<16) /* USB Power Sense Port 3 */
842: #define USBHC_HIT_MASK (USBHC_HIT_RWUT | USBHC_HIT_BAT | \
843: USBHC_HIT_IRQT | USBHC_HIT_TAT | USBHC_HIT_UPS1T | USBHC_HIT_UPS2T | \
844: USBHC_HIT_UPRT | USBHC_HIT_STAT | USBHC_HIT_SMAT | USBHC_HIT_UPS3T)
845: #define USBHC_RST_WAIT 10000 /* usecs to wait for reset */
846:
847: /* OS Timer */
848: #define OST_OSMR0 0x0000 /* Match 0 */
849: #define OST_OSMR1 0x0004 /* Match 1 */
850: #define OST_OSMR2 0x0008 /* Match 2 */
851: #define OST_OSMR3 0x000c /* Match 3 */
852: #define OST_OSCR0 0x0010 /* Counter 0 */
853:
854: #define OST_OSCR4 0x0040 /* Counter 4 */
855: #define OST_OMCR4 0x00c0 /* Counter 4 match control */
856: #define OST_OSMR4 0x0080 /* Counter 4 match */
857: #define OST_OSCR5 0x0044 /* Counter 5 */
858: #define OST_OMCR5 0x00c4 /* Counter 5 match control */
859: #define OST_OSMR5 0x0084 /* Counter 4 match */
860:
861: #define OST_OSSR 0x0014 /* Status (all counters) */
862: #define OST_OWER 0x0018 /* Watchdog Enable */
863: #define OWER_WME (1<<0)
864: #define OST_OIER 0x001c /* Interrupt Enable */
865: #define OIER_E3 (1<<3)
866:
867: /* Synchronous Serial Protocol (SSP) serial ports */
868: #define SSP_SSCR0 0x00
869: #define SSP_SSCR1 0x04
870: #define SSP_SSSR 0x08
871: #define SSSR_TNF (1<<2)
872: #define SSSR_RNE (1<<3)
873: #define SSP_SSDR 0x10
874:
875: #endif /* _ARM_XSCALE_PXA2X0REG_H_ */
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