Annotation of sys/arch/arm/xscale/pxa27x_udcreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: pxa27x_udcreg.h,v 1.5 2007/02/25 01:40:12 drahn Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
! 5: *
! 6: * Permission to use, copy, modify, and distribute this software for any
! 7: * purpose with or without fee is hereby granted, provided that the above
! 8: * copyright notice and this permission notice appear in all copies.
! 9: *
! 10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
! 11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
! 12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
! 13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
! 14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
! 15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
! 16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
! 17: */
! 18:
! 19: /*
! 20: * Register Descriptions for the USB Device Controller
! 21: *
! 22: * Reference:
! 23: * Intel(r) PXA27x Processor Family
! 24: * Developer's Manual
! 25: * (2800002.pdf)
! 26: */
! 27:
! 28: #ifndef _ARM_XSCALE_PXA27X_UDCREG_H_
! 29: #define _ARM_XSCALE_PXA27X_UDCREG_H_
! 30:
! 31: #define USBDC_UDCCR 0x0000 /* UDC Control Register */
! 32: #define USBDC_UDCCR_UDE (1<<0) /* UDC Enable */
! 33: #define USBDC_UDCCR_UDA (1<<1) /* UDC Active */
! 34: #define USBDC_UDCCR_UDR (1<<2) /* UDC Resume */
! 35: #define USBDC_UDCCR_EMCE (1<<3) /* Endpoint Mem Config Error */
! 36: #define USBDC_UDCCR_SMAC (1<<4) /* Switch EndPt Mem to Active Config */
! 37: #define USBDC_UDCCR_AAISN (7<<5) /* Active UDC Alt Iface Setting */
! 38: #define USBDC_UDCCR_AAISNr(x) ((x>>5)&7) /* Active UDC Config */
! 39: #define USBDC_UDCCR_AIN (7<<8) /* Active UDC Iface */
! 40: #define USBDC_UDCCR_AINr(x) ((x>>8)&7) /* Active UDC Config */
! 41: #define USBDC_UDCCR_ACN (7<<11) /* Active UDC Config */
! 42: #define USBDC_UDCCR_ACNr(x) ((x>>11)&7) /* Active UDC Config */
! 43: #define USBDC_UDCCR_DWRE (1<<16) /* Device Remote Wake-Up Feature */
! 44: #define USBDC_UDCCR_BHNP (1<<28) /* B-Device Host Neg Proto Enable */
! 45: #define USBDC_UDCCR_AHNP (1<<29) /* A-Device Host NEg Proto Support */
! 46: #define USBDC_UDCCR_AALTHNP (1<<30) /* A-Dev Alt Host Neg Proto Port Sup */
! 47: #define USBDC_UDCCR_OEN (1<<31) /* On-The-Go Enable */
! 48: #define USBDC_UDCICR0 0x0004 /* UDC Interrupt Control Register 0 */
! 49: #define USBDC_UDCICR0_IE(n) (3<<((n)*2)) /* Interrupt Enables */
! 50: #define USBDC_UDCICR1 0x0008 /* UDC Interrupt Control Register 1 */
! 51: #define USBDC_UDCICR1_IE(n) (3<<((n)*2)) /* Interrupt Enables */
! 52: #define USBDC_UDCICR1_IERS (1<<27) /* Interrupt Enable Reset */
! 53: #define USBDC_UDCICR1_IESU (1<<28) /* Interrupt Enable Suspend */
! 54: #define USBDC_UDCICR1_IERU (1<<29) /* Interrupt Enable Resume */
! 55: #define USBDC_UDCICR1_IESOF (1<<30) /* Interrupt Enable Start of Frame */
! 56: #define USBDC_UDCICR1_IECC (1<<31) /* Interrupt Enable Config Change */
! 57: #define USBDC_UDCISR0 0x000c /* UDC Interrupt Status Register 0 */
! 58: #define USBDC_UDCISR0_IR(n) (3<<((n)*2)) /* Interrupt Requests */
! 59: #define USBDC_UDCISR0_IRs(v,n) (((v)>>((n)*2))&3) /* Interrupt Requests */
! 60: #define USBDC_UDCISR1 0x0010 /* UDC Interrupt Status Register 1 */
! 61: #define USBDC_UDCISR1_IR(n) (3<<((n)*2)) /* Interrupt Requests */
! 62: #define USBDC_UDCISR1_IRs(v,n) (((v)>>((n)*2))&3) /* Interrupt Requests */
! 63: #define USBDC_UDCISR1_IRRS (1<<27) /* Interrupt Enable Reset */
! 64: #define USBDC_UDCISR1_IRSU (1<<28) /* Interrupt Enable Suspend */
! 65: #define USBDC_UDCISR1_IRRU (1<<29) /* Interrupt Enable Resume */
! 66: #define USBDC_UDCISR1_IRSOF (1<<30) /* Interrupt Enable Start of Frame */
! 67: #define USBDC_UDCISR1_IRCC (1<<31) /* Interrupt Enable Config Change */
! 68: #define USBDC_UDCFNR 0x0014 /* UDC Frame Number Register */
! 69: #define USBDC_UDCFNR_FN (1023<<0) /* Frame Number */
! 70: #define USBDC_UDCOTGICR 0x0018 /* UDC OTG Interrupt Control Register */
! 71: #define USBDC_UDCOTGICR_IEIDF (1<<0) /* OTG ID Change Fall Intr En */
! 72: #define USBDC_UDCOTGICR_IEIDR (1<<1) /* OTG ID Change Ris Intr En */
! 73: #define USBDC_UDCOTGICR_IESDF (1<<2) /* OTG A-Dev SRP Detect Fall Intr En */
! 74: #define USBDC_UDCOTGICR_IESDR (1<<3) /* OTG A-Dev SRP Detect Ris Intr En */
! 75: #define USBDC_UDCOTGICR_IESVF (1<<4) /* OTG Session Valid Fall Intr En */
! 76: #define USBDC_UDCOTGICR_IESVR (1<<5) /* OTG Session Valid Ris Intr En */
! 77: #define USBDC_UDCOTGICR_IEVV44F (1<<6) /* OTG Vbus Valid 4.4V Fall Intr En */
! 78: #define USBDC_UDCOTGICR_IEVV44R (1<<7) /* OTG Vbus Valid 4.4V Ris Intr En */
! 79: #define USBDC_UDCOTGICR_IEVV40F (1<<8) /* OTG Vbus Valid 4.0V Fall Intr En */
! 80: #define USBDC_UDCOTGICR_IEVV40R (1<<9) /* OTG Vbus Valid 4.0V Ris Intr En */
! 81: #define USBDC_UDCOTGICR_IEXF (1<<16) /* Extern Transceiver Intr Fall En */
! 82: #define USBDC_UDCOTGICR_IEXR (1<<17) /* Extern Transceiver Intr Ris En */
! 83: #define USBDC_UDCOTGICR_IESF (1<<24) /* OTG SET_FEATURE Command Recvd */
! 84: #define USBDC_UDCOTGISR 0x001c /* UDC OTG Interrupt Status Register */
! 85: #define USBDC_UDCOTGISR_IRIDF (1<<0) /* OTG ID Change Fall Intr Req */
! 86: #define USBDC_UDCOTGISR_IRIDR (1<<1) /* OTG ID Change Ris Intr Req */
! 87: #define USBDC_UDCOTGISR_IRSDF (1<<2) /* OTG A-Dev SRP Detect Fall Intr Req */
! 88: #define USBDC_UDCOTGISR_IRSDR (1<<3) /* OTG A-Dev SRP Detect Ris Intr Req */
! 89: #define USBDC_UDCOTGISR_IRSVF (1<<4) /* OTG Session Valid Fall Intr Req */
! 90: #define USBDC_UDCOTGISR_IRSVR (1<<5) /* OTG Session Valid Ris Intr Req */
! 91: #define USBDC_UDCOTGISR_IRVV44F (1<<6) /* OTG Vbus Valid 4.4V Fall Intr Req */
! 92: #define USBDC_UDCOTGISR_IRVV44R (1<<7) /* OTG Vbus Valid 4.4V Ris Intr Req */
! 93: #define USBDC_UDCOTGISR_IRVV40F (1<<8) /* OTG Vbus Valid 4.0V Fall Intr Req */
! 94: #define USBDC_UDCOTGISR_IRVV40R (1<<9) /* OTG Vbus Valid 4.0V Ris Intr Req */
! 95: #define USBDC_UDCOTGISR_IRXF (1<<16) /* Extern Transceiver Intr Fall Req */
! 96: #define USBDC_UDCOTGISR_IRXR (1<<17) /* Extern Transceiver Intr Ris Req */
! 97: #define USBDC_UDCOTGISR_IRSF (1<<24) /* OTG SET_FEATURE Command Recvd */
! 98: #define USBDC_UP2OCR 0x0020 /* USB Port 2 Output Control Register */
! 99: #define USBDC_UP2OCR_CPVEN (1<<0) /* Charge Pump Vbus Enable */
! 100: #define USBDC_UP2OCR_CPVPE (1<<1) /* Charge Pump Vbus Pulse Enable */
! 101: #define USBDC_UP2OCR_DPPDE (1<<2) /* Host Transc D+ Pull Down En */
! 102: #define USBDC_UP2OCR_DMPDE (1<<3) /* Host Transc D- Pull Down En */
! 103: #define USBDC_UP2OCR_DPPUE (1<<4) /* Host Transc D+ Pull Up En */
! 104: #define USBDC_UP2OCR_DMPUE (1<<5) /* Host Transc D- Pull Up En */
! 105: #define USBDC_UP2OCR_DPPUBE (1<<6) /* Host Transc D+ Pull Up Bypass En */
! 106: #define USBDC_UP2OCR_DMPUBE (1<<7) /* Host Transc D- Pull Up Bypass En */
! 107: #define USBDC_UP2OCR_EXSP (1<<8) /* External Transc Speed Control */
! 108: #define USBDC_UP2OCR_EXSUS (1<<9) /* External Transc Suspend Control */
! 109: #define USBDC_UP2OCR_IDON (1<<10) /* OTG ID Read Enable */
! 110: #define USBDC_UP2OCR_HXS (1<<16) /* Host Transc Output Select */
! 111: #define USBDC_UP2OCR_HXOE (1<<17) /* Host Transc Output Enable */
! 112: #define USBDC_UP2OCR_SEOS (7<<24) /* Single-Ended Output Select */
! 113: #define USBDC_UP3OCR 0x0024 /* USB Port 3 Output Control Register */
! 114: #define USBDC_UP3OCR_CFG (3<<0) /* Host Port Configuration */
! 115: /* 0x0028 to 0x00fc is reserved */
! 116: #define USBDC_UDCCSR0 0x0100 /* UDC Endpoint 0 Control/Status Registers */
! 117: #define USBDC_UDCCSR0_OPC (1<<0) /* OUT Packet Complete */
! 118: #define USBDC_UDCCSR0_IPR (1<<1) /* IN Packet Ready */
! 119: #define USBDC_UDCCSR0_FTF (1<<2) /* Flush Transmit FIFO */
! 120: #define USBDC_UDCCSR0_DME (1<<3) /* DMA Enable */
! 121: #define USBDC_UDCCSR0_SST (1<<4) /* Sent Stall */
! 122: #define USBDC_UDCCSR0_FST (1<<5) /* Force Stall */
! 123: #define USBDC_UDCCSR0_RNE (1<<6) /* Receive FIFO Not Empty */
! 124: #define USBDC_UDCCSR0_SA (1<<7) /* Setup Active */
! 125: #define USBDC_UDCCSR0_AREN (1<<8) /* ACK Response Enable */
! 126: #define USBDC_UDCCSR0_ACM (1<<9) /* ACK Control Mode */
! 127: #define USBDC_UDCCSR(n) (0x0100+4*(n)) /* UDC Control/Status Registers */
! 128: #define USBDC_UDCCSR_FS (1<<0) /* FIFO Needs Service */
! 129: #define USBDC_UDCCSR_PC (1<<1) /* Packet Complete */
! 130: #define USBDC_UDCCSR_TRN (1<<2) /* Tx/Rx NAK */
! 131: #define USBDC_UDCCSR_DME (1<<3) /* DMA Enable */
! 132: #define USBDC_UDCCSR_SST (1<<4) /* Sent STALL */
! 133: #define USBDC_UDCCSR_FST (1<<5) /* Force STALL */
! 134: #define USBDC_UDCCSR_BNE (1<<6) /* OUT: Buffer Not Empty */
! 135: #define USBDC_UDCCSR_BNF (1<<6) /* IN: Buffer Not Full */
! 136: #define USBDC_UDCCSR_SP (1<<7) /* Short Packet Control/Status */
! 137: #define USBDC_UDCCSR_FEF (1<<8) /* Flush Endpoint FIFO */
! 138: #define USBDC_UDCCSR_DPE (1<<9) /* Data Packet Empty (async EP only) */
! 139: /* 0x0160 to 0x01fc is reserved */
! 140: #define USBDC_UDCBCR(n) (0x0200+4*(n)) /* UDC Byte Count Registers */
! 141: #define USBDC_UDCBCR_BC (1023<<0) /* Byte Count */
! 142: /* 0x0260 to 0x02fc is reserved */
! 143: #define USBDC_UDCDR(n) (0x0300+4*(n)) /* UDC Data Registers */
! 144: /* 0x0360 to 0x03fc is reserved */
! 145: /* 0x0400 is reserved */
! 146: #define USBDC_UDCECR(n) (0x0400+4*(n)) /* UDC Configuration Registers */
! 147: #define USBDC_UDCECR_EE (1<<0) /* Endpoint Enable */
! 148: #define USBDC_UDCECR_DE (1<<1) /* Double-Buffering Enable */
! 149: #define USBDC_UDCECR_MPS (1023<<2) /* Maximum Packet Size */
! 150: #define USBDC_UDCECR_ED (1<<12) /* USB Endpoint Direction 0 OUT, 1 IN */
! 151: #define USBDC_UDCECR_ET (3<<13) /* USB Enpoint Type */
! 152: #define USBDC_UDCECR_EN (15<<15) /* Endpoint Number */
! 153: #define USBDC_UDCECR_AISN (7<<19) /* Alternate Interface Number */
! 154: #define USBDC_UDCECR_IN (7<<22) /* Interface Number */
! 155: #define USBDC_UDCECR_CN (3<<25) /* Configuration Number */
! 156:
! 157: #define USBDC_UDCECR_MPSs(n) ((n)<<2) /* Maximum Packet Size */
! 158: #define USBDC_UDCECR_ETs(n) ((n)<<13) /* USB Enpoint Type */
! 159: #define USBDC_UDCECR_ET_INT 3
! 160: #define USBDC_UDCECR_ET_BULK 2
! 161: #define USBDC_UDCECR_ET_ISO 1
! 162: #define USBDC_UDCECR_ENs(n) ((n)<<15) /* Endpoint Number */
! 163: #define USBDC_UDCECR_AISNs(n) ((n)<<19) /* Alternate Interface Number */
! 164: #define USBDC_UDCECR_INs(n) ((n)<<22) /* Interface Number */
! 165: #define USBDC_UDCECR_CNs(n) ((n)<<25) /* Configuration Number */
! 166:
! 167: #define USBDC_UDCCR_BITS \
! 168: "\20\001UDE\002UDA\003UDR\004EMCE\005SMAC\021DWRE" \
! 169: "\035BHNP\036AHNP\037OEN"
! 170: #define USBDC_UDCISR0_BITS \
! 171: "\20\0010P\0020F\003AP\004AF\005BP\006BF\007CP\010CF" \
! 172: "\011DP\012DF\013EP\014EF\015FP\016FF\017GP\020GF" \
! 173: "\031HP\032HF\033IP\034IF\035JP\036JF\037KP\030KF" \
! 174: "\041LP\042LF\043MP\044MF\045NP\046NF\047PP\040PF"
! 175: #define USBDC_UDCISR1_BITS \
! 176: "\20\001QP\002QF\003RP\004RF\005SP\006SF\007TP\010TF" \
! 177: "\011UP\012UF\013VP\014VF\015WP\016WF\017XP\020XF" \
! 178: "\034RS\035SU\036RU\037SOF\040CC"
! 179: #define USBDC_UDCOTGISR_BITS \
! 180: "\20\001IRIDF\002IRIDR\003IRSDF\004IRSDR\005IRSVF\006IRSVR" \
! 181: "\007IRVV44F\010IRVV44R\011IRVV40F\012IRVV40R"
! 182: #define USBDC_UDCCSR0_BITS \
! 183: "\20\001OPC\002IPR\003FTF\004DME\005SST\006FST\007RNE" \
! 184: "\010SA\011AREN\012ACM"
! 185: #define USBDC_UDCCSRN_BITS \
! 186: "\20\001FS\002PC\003TRN\004DME\005SST\006FST\007BNEF" \
! 187: "\010SP\011FEF\012DPE"
! 188:
! 189: #endif /* _ARM_XSCALE_PXA27X_UDCREG_H_ */
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