Annotation of sys/arch/arm/xscale/i80321var.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: i80321var.h,v 1.3 2006/06/15 21:35:30 drahn Exp $ */
2: /* $NetBSD: i80321var.h,v 1.10 2005/12/15 01:44:00 briggs Exp $ */
3:
4: /*
5: * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
6: * All rights reserved.
7: *
8: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed for the NetBSD Project by
21: * Wasabi Systems, Inc.
22: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23: * or promote products derived from this software without specific prior
24: * written permission.
25: *
26: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36: * POSSIBILITY OF SUCH DAMAGE.
37: */
38:
39: #ifndef _ARM_XSCALE_I80321VAR_H_
40: #define _ARM_XSCALE_I80321VAR_H_
41:
42: #include <sys/queue.h>
43: #include <sys/gpio.h>
44: #include <sys/evcount.h>
45: #include <dev/pci/pcivar.h>
46: #include <dev/gpio/gpiovar.h>
47:
48: /*
49: * There are roughly 32 interrupt sources.
50: */
51: #define NIRQ 32
52:
53: struct intrhand {
54: TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
55: int (*ih_func)(void *); /* handler */
56: void *ih_arg; /* arg for handler */
57: int ih_ipl; /* IPL_* */
58: int ih_irq; /* IRQ number */
59: struct evcount ih_count;
60: char *ih_name;
61: };
62:
63: struct intrq {
64: TAILQ_HEAD(, intrhand) iq_list; /* handler list */
65: int iq_irq; /* IRQ to mask while handling */
66: int iq_levels; /* IPL_*'s this IRQ has */
67: int iq_ist; /* share type */
68: };
69:
70: struct config_bus_space {
71: u_int32_t bus_base;
72: u_int32_t bus_size;
73: int bus_io;
74: };
75:
76: struct i80321_softc {
77: struct device sc_dev; /* generic device glue */
78:
79: int sc_is_host; /* indicates if we're a host or
80: plugged into another host */
81:
82: /*
83: * This is the bus_space and handle used to access the
84: * i80321 itself. This is filled in by the board-specific
85: * front-end.
86: */
87: bus_space_tag_t sc_st;
88: bus_space_handle_t sc_sh;
89:
90: /* Handles for the various subregions. */
91: bus_space_handle_t sc_atu_sh;
92: bus_space_handle_t sc_mcu_sh;
93:
94: #ifdef BULLSHIT
95: /*
96: * We expect the board-specific front-end to have already mapped
97: * the PCI I/O space .. it is only 64K, and I/O mappings tend to
98: * be smaller than a page size, so it's generally more efficient
99: * to map them all into virtual space in one fell swoop.
100: */
101: vaddr_t sc_iow_vaddr; /* I/O window vaddr */
102: #else
103: bus_space_handle_t sc_io_sh;
104: #endif
105:
106: /*
107: * Variables that define the Inbound windows. The base address of
108: * 0-2 are configured by a host via BARs. The xlate variable
109: * defines the start of the local address space that it maps to.
110: * The size variable defines the byte size.
111: *
112: * The first 3 windows are for incoming PCI memory read/write
113: * cycles from a host. The 4th window, not configured by the
114: * host (as it outside the normal BAR range) is the inbound
115: * window for PCI devices controlled by the i80321.
116: */
117: struct {
118: uint32_t iwin_base_hi;
119: uint32_t iwin_base_lo;
120: uint32_t iwin_xlate;
121: uint32_t iwin_size;
122: } sc_iwin[4];
123:
124: /*
125: * Variables that define the Outbound windows.
126: */
127: struct {
128: uint32_t owin_xlate_lo;
129: uint32_t owin_xlate_hi;
130: } sc_owin[2];
131:
132: /*
133: * This is the PCI address that the Outbound I/O window maps to.
134: * The offset is to keep the actual used I/O address away from 0,
135: * which can be bad if, say, an i8254x gig-e chip gets mapped there.
136: * The 0 value apparently looks like "unconfigured" to the controller
137: * and it ignores writes to that region (it doesn't cause a bus fault,
138: * it just ignores them--leading to a non-functional controller). The
139: * wm(4) driver usually uses memory-mapped regions, but does use the
140: * I/O-mapped region for reset operations in order to work around a
141: * bug in the chip.
142: * Iyonix, while using sc_ioout_xlate 0 needs an offset of 0, too, in
143: * order to function properly. These values are both set in the
144: * port-specific i80321_mainbus_attach() routine.
145: */
146: uint32_t sc_ioout_xlate;
147: uint32_t sc_ioout_xlate_offset;
148:
149: /* Bus space, DMA, and PCI tags for the PCI bus (private devices). */
150: struct bus_space sc_pci_iot;
151: struct bus_space sc_pci_memt;
152: struct arm32_bus_dma_tag sc_pci_dmat;
153: struct arm32_pci_chipset sc_pci_chipset;
154:
155: /* DMA window info for PCI DMA. */
156: struct arm32_dma_range sc_pci_dma_range;
157:
158: /* GPIO state */
159: uint8_t sc_gpio_dir; /* GPIO pin direction (1 == output) */
160: uint8_t sc_gpio_val; /* GPIO output pin value */
161:
162: #define I80219_GPIO_NPINS 8
163: /* GPIO for 80219 -XXX */
164: struct gpio_chipset_tag sc_gpio_gc;
165: struct gpio_pin sc_gpio_pins[I80219_GPIO_NPINS];
166:
167: /* DMA tag for local devices. */
168: struct arm32_bus_dma_tag sc_local_dmat;
169:
170: /* Structures to do bus fixup */
171: int nbogus;
172: struct extent *extent_mem;
173: struct extent *extent_port;
174: struct config_bus_space sc_membus_space;
175: struct config_bus_space sc_iobus_space;
176:
177:
178: };
179:
180: /*
181: * Arguments used to attach IOP built-ins.
182: */
183: struct iopxs_attach_args {
184: const char *ia_name; /* name of device */
185: bus_space_tag_t ia_st; /* space tag */
186: bus_space_handle_t ia_sh;/* handle of IOP base */
187: bus_dma_tag_t ia_dmat; /* DMA tag */
188: bus_addr_t ia_offset; /* offset of device from IOP base */
189: bus_size_t ia_size; /* size of sub-device */
190: };
191:
192: extern struct bus_space i80321_bs_tag;
193: extern struct i80321_softc *i80321_softc;
194:
195: extern void (*i80321_hardclock_hook)(void);
196:
197: void i80321_sdram_bounds(bus_space_tag_t, bus_space_handle_t,
198: paddr_t *, psize_t *);
199:
200: void i80321_calibrate_delay(void);
201:
202: void i80321intc_init(void);
203: void i80321intc_intr_init(void);
204: void *i80321intc_establish(int, int, int (*)(void *), void *, char *);
205: void i80321intc_disestablish(void *);
206:
207: void i80321_gpio_set_direction(uint8_t, uint8_t);
208: void i80321_gpio_set_val(uint8_t, uint8_t);
209: uint8_t i80321_gpio_get_val(void);
210:
211: void i80321_bs_init(bus_space_tag_t, void *);
212: void i80321_io_bs_init(bus_space_tag_t, void *);
213: void i80321_mem_bs_init(bus_space_tag_t, void *);
214:
215: void i80321_local_dma_init(struct i80321_softc *sc);
216:
217: void i80321_pci_init(pci_chipset_tag_t, void *);
218:
219: void i80321_attach(struct i80321_softc *);
220: #endif /* _ARM_XSCALE_I80321VAR_H_ */
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