Annotation of sys/arch/arm/xscale/i80321.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: i80321.c,v 1.5 2006/12/14 17:36:12 kettenis Exp $ */
2: /* $NetBSD: i80321.c,v 1.18 2006/02/25 02:28:56 wiz Exp $ */
3:
4: /*
5: * Copyright (c) 2002 Wasabi Systems, Inc.
6: * All rights reserved.
7: *
8: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed for the NetBSD Project by
21: * Wasabi Systems, Inc.
22: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23: * or promote products derived from this software without specific prior
24: * written permission.
25: *
26: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36: * POSSIBILITY OF SUCH DAMAGE.
37: */
38:
39: /*
40: * Autoconfiguration support for the Intel i80321 I/O Processor.
41: */
42:
43: #include <sys/param.h>
44: #include <sys/systm.h>
45: #include <sys/device.h>
46:
47: #define _ARM32_BUS_DMA_PRIVATE
48: #include <machine/bus.h>
49:
50: #include <arm/xscale/i80321reg.h>
51: #include <arm/xscale/i80321var.h>
52:
53: /*
54: * Statically-allocated bus_space structure used to access the
55: * i80321's own registers.
56: */
57: struct bus_space i80321_bs_tag;
58:
59: /*
60: * There can be only one i80321, so we keep a global pointer to
61: * the softc, so board-specific code can use features of the
62: * i80321 without having to have a handle on the softc itself.
63: */
64: struct i80321_softc *i80321_softc;
65:
66: static int i80321_iopxs_print(void *, const char *);
67:
68: /* Built-in devices. */
69: static const struct iopxs_device {
70: const char *id_name;
71: bus_addr_t id_offset;
72: bus_size_t id_size;
73: } iopxs_devices[] = {
74: { "iopaau", VERDE_AAU_BASE, VERDE_AAU_SIZE },
75: /* { "iopdma", VERDE_DMA_BASE0, VERDE_DMA_CHSIZE }, */
76: /* { "iopdma", VERDE_DMA_BASE1, VERDE_DMA_CHSIZE }, */
77: { "iopiic", VERDE_I2C_BASE0, VERDE_I2C_CHSIZE },
78: { "iopiic", VERDE_I2C_BASE1, VERDE_I2C_CHSIZE },
79: /* { "iopssp", VERDE_SSP_BASE, VERDE_SSP_SIZE }, */
80: { "iopmu", VERDE_MU_BASE, VERDE_MU_SIZE },
81: { "iopwdog", 0, 0 },
82: { NULL, 0, 0 }
83: };
84:
85: static void i80321_pci_dma_init(struct i80321_softc *);
86:
87: /* XXX - debug */
88: /*
89: * i80321_attach:
90: *
91: * Board-independent attach routine for the i80321.
92: */
93: void
94: i80321_attach(struct i80321_softc *sc)
95: {
96: struct pcibus_attach_args pba;
97: const struct iopxs_device *id;
98: struct iopxs_attach_args ia;
99: pcireg_t preg;
100:
101: i80321_softc = sc;
102:
103: /*
104: * Program the Inbound windows.
105: */
106: bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0,
107: (0xffffffff - (sc->sc_iwin[0].iwin_size - 1)) & 0xffffffc0);
108: bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR0,
109: sc->sc_iwin[0].iwin_xlate);
110:
111: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
112: PCI_MAPREG_START, sc->sc_iwin[0].iwin_base_lo);
113: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
114: PCI_MAPREG_START + 0x04, sc->sc_iwin[0].iwin_base_hi);
115:
116: bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1,
117: (0xffffffff - (sc->sc_iwin[1].iwin_size - 1)) & 0xffffffc0);
118: /* no xlate for window 1 */
119:
120: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
121: PCI_MAPREG_START + 0x08, sc->sc_iwin[1].iwin_base_lo);
122: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
123: PCI_MAPREG_START + 0x0c, sc->sc_iwin[1].iwin_base_hi);
124:
125: bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2,
126: (0xffffffff - (sc->sc_iwin[2].iwin_size - 1)) & 0xffffffc0);
127: bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR2,
128: sc->sc_iwin[2].iwin_xlate);
129:
130: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
131: PCI_MAPREG_START + 0x10, sc->sc_iwin[2].iwin_base_lo);
132: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
133: PCI_MAPREG_START + 0x14, sc->sc_iwin[2].iwin_base_hi);
134:
135: bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR3,
136: (0xffffffff - (sc->sc_iwin[3].iwin_size - 1)) & 0xffffffc0);
137: bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR3,
138: sc->sc_iwin[3].iwin_xlate);
139:
140: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
141: ATU_IABAR3, sc->sc_iwin[3].iwin_base_lo);
142: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
143: ATU_IAUBAR3, sc->sc_iwin[3].iwin_base_hi);
144:
145: /*
146: * Mask (disable) the ATU interrupt sources.
147: * XXX May want to revisit this if we encounter
148: * XXX an application that wants it.
149: */
150: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
151: ATU_ATUIMR,
152: ATUIMR_IMW1BU|ATUIMR_ISCEM|ATUIMR_RSCEM|ATUIMR_PST|
153: ATUIMR_DPE|ATUIMR_P_SERR_ASRT|ATUIMR_PMA|ATUIMR_PTAM|
154: ATUIMR_PTAT|ATUIMR_PMPE);
155:
156: /*
157: * Program the outbound windows.
158: */
159: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
160: ATU_OIOWTVR, sc->sc_ioout_xlate);
161:
162: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
163: ATU_OMWTVR0, sc->sc_owin[0].owin_xlate_lo);
164: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
165: ATU_OUMWTVR0, sc->sc_owin[0].owin_xlate_hi);
166:
167: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
168: ATU_OMWTVR1, sc->sc_owin[1].owin_xlate_lo);
169: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
170: ATU_OUMWTVR1, sc->sc_owin[1].owin_xlate_hi);
171:
172: /*
173: * Set up the ATU configuration register. All we do
174: * right now is enable Outbound Windows.
175: */
176: bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUCR,
177: ATUCR_OUT_EN);
178:
179: /*
180: * Enable bus mastering, memory access, SERR, and parity
181: * checking on the ATU.
182: */
183: preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
184: PCI_COMMAND_STATUS_REG);
185: preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE |
186: PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
187: bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
188: PCI_COMMAND_STATUS_REG, preg);
189:
190: /* Initialize the bus space tags. */
191: i80321_io_bs_init(&sc->sc_pci_iot, sc);
192: i80321_mem_bs_init(&sc->sc_pci_memt, sc);
193:
194: /* Initialize the DMA tags. */
195: i80321_pci_dma_init(sc);
196: i80321_local_dma_init(sc);
197:
198: /*
199: * Attach all the IOP built-ins.
200: */
201: for (id = iopxs_devices; id->id_name != NULL; id++) {
202: ia.ia_name = id->id_name;
203: ia.ia_st = sc->sc_st;
204: ia.ia_sh = sc->sc_sh;
205: ia.ia_dmat = &sc->sc_local_dmat;
206: ia.ia_offset = id->id_offset;
207: ia.ia_size = id->id_size;
208:
209: config_found(&sc->sc_dev, &ia, i80321_iopxs_print);
210: }
211:
212: /*
213: * Attach the PCI bus.
214: */
215: preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
216: preg = PCIXSR_BUSNO(preg);
217: if (preg == 0xff)
218: preg = 0;
219: pba.pba_busname = "pci";
220: pba.pba_iot = &sc->sc_pci_iot;
221: pba.pba_memt = &sc->sc_pci_memt;
222: pba.pba_dmat = &sc->sc_pci_dmat;
223: pba.pba_pc = &sc->sc_pci_chipset;
224: pba.pba_domain = pci_ndomains++;
225: pba.pba_bus = preg;
226: pba.pba_bridgetag = NULL;
227: pba.pba_intrswiz = 0; /* XXX what if busno != 0? */
228: pba.pba_intrtag = 0;
229:
230: config_found((struct device *)sc, &pba, i80321_iopxs_print);
231: }
232:
233: /*
234: * i80321_iopxs_print:
235: *
236: * Autoconfiguration cfprint routine when attaching
237: * to the "iopxs" device.
238: */
239: static int
240: i80321_iopxs_print(void *aux, const char *pnp)
241: {
242:
243: return (QUIET);
244: }
245:
246: /*
247: * i80321_pci_dma_init:
248: *
249: * Initialize the PCI DMA tag.
250: */
251: static void
252: i80321_pci_dma_init(struct i80321_softc *sc)
253: {
254: bus_dma_tag_t dmat = &sc->sc_pci_dmat;
255: struct arm32_dma_range *dr = &sc->sc_pci_dma_range;
256:
257: dr->dr_sysbase = sc->sc_iwin[2].iwin_xlate;
258: dr->dr_busbase = PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo);
259: dr->dr_len = sc->sc_iwin[2].iwin_size;
260:
261: dmat->_ranges = dr;
262: dmat->_nranges = 1;
263:
264: dmat->_dmamap_create = _bus_dmamap_create;
265: dmat->_dmamap_destroy = _bus_dmamap_destroy;
266: dmat->_dmamap_load = _bus_dmamap_load;
267: dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
268: dmat->_dmamap_load_uio = _bus_dmamap_load_uio;
269: dmat->_dmamap_load_raw = _bus_dmamap_load_raw;
270: dmat->_dmamap_unload = _bus_dmamap_unload;
271: dmat->_dmamap_sync = _bus_dmamap_sync;
272:
273: dmat->_dmamem_alloc = _bus_dmamem_alloc;
274: dmat->_dmamem_free = _bus_dmamem_free;
275: dmat->_dmamem_map = _bus_dmamem_map;
276: dmat->_dmamem_unmap = _bus_dmamem_unmap;
277: dmat->_dmamem_mmap = _bus_dmamem_mmap;
278: }
279:
280: /*
281: * i80321_local_dma_init:
282: *
283: * Initialize the local DMA tag.
284: */
285: void
286: i80321_local_dma_init(struct i80321_softc *sc)
287: {
288: bus_dma_tag_t dmat = &sc->sc_local_dmat;
289:
290: dmat->_ranges = NULL;
291: dmat->_nranges = 0;
292:
293: dmat->_dmamap_create = _bus_dmamap_create;
294: dmat->_dmamap_destroy = _bus_dmamap_destroy;
295: dmat->_dmamap_load = _bus_dmamap_load;
296: dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
297: dmat->_dmamap_load_uio = _bus_dmamap_load_uio;
298: dmat->_dmamap_load_raw = _bus_dmamap_load_raw;
299: dmat->_dmamap_unload = _bus_dmamap_unload;
300: dmat->_dmamap_sync = _bus_dmamap_sync;
301:
302: dmat->_dmamem_alloc = _bus_dmamem_alloc;
303: dmat->_dmamem_free = _bus_dmamem_free;
304: dmat->_dmamem_map = _bus_dmamem_map;
305: dmat->_dmamem_unmap = _bus_dmamem_unmap;
306: dmat->_dmamem_mmap = _bus_dmamem_mmap;
307: }
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