Return to sa11x0_reg.h CVS log

Up to [local] / sys / arch / arm / sa11x0

Annotation of sys/arch/arm/sa11x0/sa11x0_reg.h, Revision 1.1

1.1     ! nbrk        1: /*     $OpenBSD: sa11x0_reg.h,v 1.2 2005/01/02 19:52:36 drahn Exp $ */
        !             2: /*     $NetBSD: sa11x0_reg.h,v 1.4 2002/07/19 18:26:56 ichiro Exp $    */
        !             3:
        !             4: /*-
        !             5:  * Copyright (c) 2001 The NetBSD Foundation, Inc.  All rights reserved.
        !             6:  *
        !             7:  * This code is derived from software contributed to The NetBSD Foundation
        !             8:  * by IWAMOTO Toshihiro.
        !             9:  *
        !            10:  * Redistribution and use in source and binary forms, with or without
        !            11:  * modification, are permitted provided that the following conditions
        !            12:  * are met:
        !            13:  * 1. Redistributions of source code must retain the above copyright
        !            14:  *    notice, this list of conditions and the following disclaimer.
        !            15:  * 2. Redistributions in binary form must reproduce the above copyright
        !            16:  *    notice, this list of conditions and the following disclaimer in the
        !            17:  *    documentation and/or other materials provided with the distribution.
        !            18:  * 3. All advertising materials mentioning features or use of this software
        !            19:  *    must display the following acknowledgement:
        !            20:  *     This product includes software developed by the NetBSD
        !            21:  *     Foundation, Inc. and its contributors.
        !            22:  * 4. Neither the name of The NetBSD Foundation nor the names of its
        !            23:  *    contributors may be used to endorse or promote products derived
        !            24:  *    from this software without specific prior written permission.
        !            25:  *
        !            26:  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
        !            27:  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
        !            28:  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
        !            29:  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
        !            30:  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
        !            31:  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
        !            32:  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
        !            33:  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
        !            34:  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
        !            35:  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
        !            36:  * POSSIBILITY OF SUCH DAMAGE.
        !            37:  */
        !            38:
        !            39: #ifndef _ARM_SA11X0_REG_H_
        !            40: #define _ARM_SA11X0_REG_H_
        !            41:
        !            42: /* Physical register base addresses */
        !            43: #define SAOST_BASE             0x90000000      /* OS Timer */
        !            44: #define SARTC_BASE             0x90010000      /* Real-Time Clock */
        !            45: #define SAPMR_BASE             0x90020000      /* Power Manager */
        !            46: #define SARCR_BASE             0x90030000      /* Reset Controller */
        !            47: #define SAGPIO_BASE            0x90040000      /* GPIO */
        !            48: #define SAIPIC_BASE            0x90050000      /* Interrupt Controller */
        !            49: #define SAPPC_BASE             0x90060000      /* Peripheral Pin Controller */
        !            50: #define SAUDC_BASE             0x80000000      /* USB Device Controller*/
        !            51: #define        SACOM1_BASE             0x80010000      /* GPCLK/UART 1 */
        !            52: #define SACOM3_HW_BASE         0x80050000      /* UART 3  */
        !            53: #define SAMCP_BASE             0x80060000      /* MCP Controller */
        !            54: #define SASSP_BASE             0x80070000      /* Synchronous serial port */
        !            55:
        !            56: #define SADMAC_BASE            0xB0000000      /* DMA Controller */
        !            57: #define SALCD_BASE             0xB0100000      /* LCD */
        !            58:
        !            59: /* Register base virtual addresses mapped by initarm() */
        !            60: //#define SACOM3_BASE             0xd000d000
        !            61: //#define SAIPIC_VBASE                 0xd000c000
        !            62: #define SACOM3_BASE             0xfd0d0000
        !            63: #define SAIPIC_VBASE                   0xfd0c0000
        !            64:
        !            65:
        !            66: /* Interrupt controller registers */
        !            67: #define SAIPIC_NPORTS          9
        !            68: #define SAIPIC_IP              0x00            /* IRQ pending register */
        !            69: #define SAIPIC_MR              0x04            /* Mask register */
        !            70: #define SAIPIC_LR              0x08            /* Level register */
        !            71: #define SAIPIC_FP              0x10            /* FIQ pending register */
        !            72: #define SAIPIC_PR              0x20            /* Pending register */
        !            73: #define SAIPIC_CR              0x0C            /* Control register */
        !            74:
        !            75: /* width of interrupt controller */
        !            76: #define ICU_LEN                        32
        !            77:
        !            78: /* Reset controller registers */
        !            79: #define SARCR_RSRR             0x0             /* Software reset register */
        !            80: #define SARCR_RCSR             0x4             /* Reset status register */
        !            81: #define SARCR_TUCR             0x8             /* Test Unit control reg */
        !            82:
        !            83: /* RTC registers */
        !            84: #define SARTC_RTAR             0x00
        !            85: #define SARTC_RCNR             0x04
        !            86: #define SARTC_RTTR             0x08
        !            87: #define SARTC_RTSR             0x10
        !            88:
        !            89: #endif /* _ARM_SA11X0_REG_H_ */