Annotation of sys/arch/arm/sa11x0/sa11x0_intr.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: pxa2x0_intr.h,v 1.11 2007/05/19 15:47:16 miod Exp $ */
2: /* $NetBSD: pxa2x0_intr.h,v 1.4 2003/07/05 06:53:08 dogcow Exp $ */
3:
4: /* Derived from i80321_intr.h */
5:
6: /*
7: * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
8: * All rights reserved.
9: *
10: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: * 3. All advertising materials mentioning features or use of this software
21: * must display the following acknowledgement:
22: * This product includes software developed for the NetBSD Project by
23: * Wasabi Systems, Inc.
24: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
25: * or promote products derived from this software without specific prior
26: * written permission.
27: *
28: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
29: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
32: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38: * POSSIBILITY OF SUCH DAMAGE.
39: */
40:
41: #ifndef _SA11X0_INTR_H_
42: #define _SA11X0_INTR_H_
43:
44: #define ARM_IRQ_HANDLER _C_LABEL(sa11x0_irq_handler)
45:
46: #ifndef _LOCORE
47:
48: #include <arm/armreg.h>
49: #include <arm/cpufunc.h>
50: #include <arm/softintr.h>
51:
52: #include <arm/sa11x0/sa11x0_var.h>
53: extern vaddr_t saic_base;
54:
55: /*
56: * Macross to read/write to memory-mapped ICU.
57: */
58: #define read_icu(offset) (*(volatile uint32_t *)(saic_base+(offset)))
59: #define write_icu(offset,value) \
60: (*(volatile uint32_t *)(saic_base+(offset))=(value))
61:
62: extern __volatile int current_spl_level;
63: extern __volatile int softint_pending;
64: extern int sa11x0_imask[];
65: void sa11x0_do_pending(void);
66:
67: void sa11x0_setipl(int new);
68: void sa11x0_splx(int new);
69: int sa11x0_splraise(int ipl);
70: int sa11x0_spllower(int ipl);
71: void sa11x0_setsoftintr(int si);
72:
73:
74: /*
75: * An useful function for interrupt handlers.
76: * XXX: This shouldn't be here.
77: */
78: static __inline int
79: find_first_bit( uint32_t bits )
80: {
81: int count;
82: uint32_t mask;
83:
84: /*
85: * If we weren't ARMv4 then we would use CLZ insn here (ARMv5 and above).
86: * Since our CPU is SA1 which is ARMv4 we implement this in software.
87: * TODO optimize code.
88: */
89: count = 0;
90: mask = 1 << 31; /* we start from MSB */
91: for (; mask > 0; mask >>= 1)
92: if (bits & mask)
93: break;
94: else
95: count++;
96:
97: return 31 - count;
98: }
99:
100:
101: int _splraise(int);
102: int _spllower(int);
103: void splx(int);
104: void _setsoftintr(int);
105:
106: /*
107: * This function *MUST* be called very early on in a port's
108: * initarm() function, before ANY spl*() functions are called.
109: *
110: * The parameter is the virtual address of the SA11x0's Interrupt
111: * Controller registers.
112: */
113: void sa11x0_intr_bootstrap(vaddr_t);
114:
115: void sa11x0_irq_handler(void *);
116: void * sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level,
117: int (*ih_fun)(void *), void *ih_arg, char *name);
118: #if 0
119: void *sa11x0_intr_establish(int irqno, int level, int (*func)(void *),
120: void *cookie, char *name);
121: #endif
122: void sa11x0_intr_disestablish(void *cookie);
123: const char *sa11x0_intr_string(void *cookie);
124:
125: #ifdef DIAGNOSTIC
126: /*
127: * Although this function is implemented in MI code, it must be in this MD
128: * header because we don't want this header to include MI includes.
129: */
130: void splassert_fail(int, int, const char *);
131: extern int splassert_ctl;
132: void sa11x0_splassert_check(int, const char *);
133: #define splassert(__wantipl) do { \
134: if (splassert_ctl > 0) { \
135: sa11x0_splassert_check(__wantipl, __func__); \
136: } \
137: } while (0)
138: #else
139: #define splassert(wantipl) do { /* nothing */ } while (0)
140: #endif
141:
142: #endif /* ! _LOCORE */
143:
144: #endif /* _SA11X0_INTR_H_ */
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