File: [local] / sys / arch / arm / sa11x0 / sa11x0_intr.c (download)
Revision 1.1.1.1 (vendor branch), Tue Mar 4 16:05:17 2008 UTC (16 years, 4 months ago) by nbrk
Branch: OPENBSD_4_2_BASE
CVS Tags: jornada-partial-support-wip Changes since 1.1: +0 -0 lines
Import of OpenBSD 4.2 release kernel tree with initial code to support
Jornada 720/728, StrongARM 1110-based handheld PC.
At this point kernel roots on NFS and boots into vfs_mountroot() and traps.
What is supported:
- glass console, Jornada framebuffer (jfb) works in 16bpp direct color mode
(needs some palette tweaks for non black/white/blue colors, i think)
- saic, SA11x0 interrupt controller (needs cleanup)
- sacom, SA11x0 UART (supported only as boot console for now)
- SA11x0 GPIO controller fully supported (but can't handle multiple interrupt
handlers on one gpio pin)
- sassp, SSP port on SA11x0 that attaches spibus
- Jornada microcontroller (jmcu) to control kbd, battery, etc throught
the SPI bus (wskbd attaches on jmcu, but not tested)
- tod functions seem work
- initial code for SA-1111 (chip companion) : this is TODO
Next important steps, i think:
- gpio and intc on sa1111
- pcmcia support for sa11x0 (and sa1111 help logic)
- REAL root on nfs when we have PCMCIA support (we may use any of supported pccard NICs)
- root on wd0! (using already supported PCMCIA-ATA)
|
/* $OpenBSD: pxa2x0_intr.c,v 1.15 2007/05/19 15:47:16 miod Exp $ */
/* $NetBSD: pxa2x0_intr.c,v 1.5 2003/07/15 00:24:55 lukem Exp $ */
/*
* Copyright (c) 2002 Genetec Corporation. All rights reserved.
* Written by Hiroyuki Bessho for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Genetec Corporation.
* 4. The name of Genetec Corporation may not be used to endorse or
* promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* IRQ handler for the Intel StrongARM SA-11[01]0 processor.
* It has integrated interrupt controller.
*/
#include <sys/cdefs.h>
/*
__KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.5 2003/07/15 00:24:55 lukem Exp $");
*/
#include <sys/cdefs.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/evcount.h>
#include <sys/queue.h>
#include <uvm/uvm_extern.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <machine/lock.h>
#include <arm/sa11x0/sa11x0_reg.h>
#include <arm/sa11x0/sa11x0_var.h>
#include <arm/sa11x0/sa11x0_intr.h>
/*
* INTC autoconf glue
*/
int saic_match(struct device *, void *, void *);
void saic_attach(struct device *, struct device *, void *);
struct cfattach saic_ca = {
sizeof(struct device), saic_match, saic_attach
};
struct cfdriver saic_cd = {
NULL, "saic", DV_DULL
};
static int saic_attached;
vaddr_t saic_base;
int sa11x0_stray_interrupt(void *);
void sa11x0_init_interrupt_masks(void);
void *_sa11x0_intr_establish(int irqno, int level,
int (*func)(void *), void *arg, char *name);
void sa11x0_intr_disestablish(void *cookie);
/* XXX defined in arch/arm/sa11x0/sa11x0_intr.h */
#define read_icu(offset) (*(volatile uint32_t *)(saic_base+(offset)))
#define write_icu(offset,value) \
(*(volatile uint32_t *)(saic_base+(offset))=(value))
/*
* interrupt dispatch table.
*/
#if 1
#define MULTIPLE_HANDLERS_ON_ONE_IRQ
#endif
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
struct intrhand {
TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
int (*ih_func)(void *); /* handler */
void *ih_arg; /* arg for handler */
char *ih_name;
struct evcount ih_count;
int ih_irq;
int ih_level;
};
#endif
static struct intrhandler{
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
TAILQ_HEAD(,intrhand) list;
#else
sa11x0_irq_handler_t func;
char *name;
void *arg; /* NULL for stackframe */
int ih_irq;
struct evcount ih_count;
#endif
} handler[ICU_LEN];
__volatile int softint_pending;
__volatile int current_spl_level;
/* interrupt masks for each level */
int sa11x0_imask[NIPL];
static int extirq_level[ICU_LEN];
int
saic_match(struct device *parent, void *cf, void *aux)
{
struct saip_attach_args *saa = aux;
if (saic_attached || saa->sai_addr != SAIPIC_BASE)
return (0);
return (1);
}
void
saic_attach(struct device *parent, struct device *self, void *args)
{
int i;
saic_attached = 1;
printf(": SA-11x0 Interrupt Controller\n");
//#define SAIPIC_ICCR 0x14 /* XXX what's this? typo or err in spec?? */
write_icu(SAIPIC_CR, 1);
write_icu(SAIPIC_MR, 0);
for(i = 0; i < sizeof handler / sizeof handler[0]; ++i){
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
TAILQ_INIT(&handler[i].list);
extirq_level[i] = IPL_NONE;
#else
handler[i].name = "stray";
handler[i].func = sa11x0_stray_interrupt;
handler[i].arg = (void *)(u_int32_t) i;
extirq_level[i] = IPL_SERIAL;
#endif
}
sa11x0_init_interrupt_masks();
_splraise(IPL_TTY);
enable_interrupts(I32_bit);
}
/*
* Invoked very early on from the board-specific initarm(), in order to
* inform us the virtual address of the interrupt controller's registers.
*/
void
sa11x0_intr_bootstrap(vaddr_t addr)
{
saic_base = addr;
}
#if 0
/*
* PXA27x has MSL interface and SSP3 interrupts [0,1], USIM interface
* and SSP2 interrupts [15,16]. PXA255 has bits [0..6,15] reserved and
* bit [16] network SSP interrupt. We don't need any of those, so we
* map software interrupts to bits [0..1,15..16]. Sadly there are no
* four contiguous bits safe enough to use on both processors.
*/
#define SI_TO_IRQBIT(si) ((si) < 2 ? 1U<<(si) : 1U<<(15-2+(si)))
#else
#define SI_TO_IRQBIT(si) (1 << (si))
#endif /* 0 */
/*
* Map a software interrupt queue to an interrupt priority level.
*/
static const int si_to_ipl[SI_NQUEUES] = {
IPL_SOFT, /* SI_SOFT */
IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
IPL_SOFTNET, /* SI_SOFTNET */
IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
};
/*
* called from irq_entry.
*/
void
sa11x0_irq_handler(void *arg)
{
struct clockframe *frame = arg;
uint32_t irqbits;
int irqno;
int saved_spl_level;
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
struct intrhand *ih;
#endif
saved_spl_level = current_spl_level;
/* get pending IRQs */
irqbits = read_icu(SAIPIC_IP);
while ((irqno = find_first_bit(irqbits)) >= 0) {
/* XXX: Should we handle IRQs in priority order? */
/* raise spl to stop interrupts of lower priorities */
if (saved_spl_level < extirq_level[irqno])
sa11x0_setipl(extirq_level[irqno]);
/* Enable interrupt */
enable_interrupts(I32_bit);
#ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ
(* handler[irqno].func)(
handler[irqno].arg == 0
? frame : handler[irqno].arg );
handler[irqno].ih_count.ec_count++;
#else
TAILQ_FOREACH(ih, &handler[irqno].list, ih_list) {
if ((ih->ih_func)( ih->ih_arg == 0
? frame : ih->ih_arg))
ih->ih_count.ec_count++;
}
#endif
/* Disable interrupt */
disable_interrupts(I32_bit);
irqbits &= ~(1<<irqno);
}
/* restore spl to that was when this interrupt happen */
sa11x0_setipl(saved_spl_level);
if(softint_pending & sa11x0_imask[current_spl_level])
sa11x0_do_pending();
}
int
sa11x0_stray_interrupt(void *cookie)
{
int irqno = (int)cookie;
printf("stray interrupt %d\n", irqno);
if (1 <= irqno && irqno < ICU_LEN){
int save = disable_interrupts(I32_bit);
write_icu(SAIPIC_MR,
read_icu(SAIPIC_MR) & ~(1U<<irqno));
restore_interrupts(save);
}
return 0;
}
/*
* Interrupt Mask Handling
*/
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
void sa11x0_update_intr_masks(void);
void
sa11x0_update_intr_masks()
#else
void sa11x0_update_intr_masks(int irqno, int level);
void
sa11x0_update_intr_masks(int irqno, int irqlevel)
#endif
{
int psw;
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
int irq;
#ifdef DEBUG
int level;
#endif
struct intrhand *ih;
psw = disable_interrupts(I32_bit);
/* First figure out which levels each IRQ uses. */
for (irq = 0; irq < ICU_LEN; irq++) {
int i;
int max = IPL_NONE;
int min = IPL_HIGH; /* XXX kill IPL_SERIAL */
TAILQ_FOREACH(ih, &handler[irq].list, ih_list) {
if (ih->ih_level > max)
max = ih->ih_level;
if (ih->ih_level < min)
min = ih->ih_level;
}
extirq_level[irq] = max;
if (min == IPL_HIGH)
min = IPL_NONE;
/* Enable interrupt at lower level */
for(i = 0; i < min; ++i)
sa11x0_imask[i] |= (1 << irq);
/* Disable interrupt at upper level */
for( ; i < NIPL-1; ++i)
sa11x0_imask[i] &= ~(1 << irq);
}
/* fixup */
sa11x0_imask[IPL_NONE] |=
SI_TO_IRQBIT(SI_SOFT) |
SI_TO_IRQBIT(SI_SOFTCLOCK) |
SI_TO_IRQBIT(SI_SOFTNET) |
SI_TO_IRQBIT(SI_SOFTSERIAL);
sa11x0_imask[IPL_SOFT] |=
SI_TO_IRQBIT(SI_SOFTCLOCK) |
SI_TO_IRQBIT(SI_SOFTNET) |
SI_TO_IRQBIT(SI_SOFTSERIAL);
sa11x0_imask[IPL_SOFTCLOCK] |=
SI_TO_IRQBIT(SI_SOFTNET) |
SI_TO_IRQBIT(SI_SOFTSERIAL);
sa11x0_imask[IPL_SOFTNET] |=
SI_TO_IRQBIT(SI_SOFTSERIAL);
sa11x0_imask[IPL_SOFTSERIAL] |=
0;
#else
int level; /* debug */
int mask = 1U<<irqno;
int i;
psw = disable_interrupts(I32_bit);
for(i = 0; i < irqlevel; ++i)
sa11x0_imask[i] |= mask; /* Enable interrupt at lower level */
for( ; i < NIPL-1; ++i)
sa11x0_imask[i] &= ~mask; /* Disable interrupt at upper level */
#endif
/*
* Enforce a hierarchy that gives "slow" device (or devices with
* limited input buffer space/"real-time" requirements) a better
* chance at not dropping data.
*/
sa11x0_imask[IPL_BIO] &= sa11x0_imask[IPL_SOFTNET];
sa11x0_imask[IPL_NET] &= sa11x0_imask[IPL_BIO];
sa11x0_imask[IPL_SOFTSERIAL] &= sa11x0_imask[IPL_NET];
sa11x0_imask[IPL_TTY] &= sa11x0_imask[IPL_SOFTSERIAL];
/*
* splvm() blocks all interrupts that use the kernel memory
* allocation facilities.
*/
sa11x0_imask[IPL_VM] &= sa11x0_imask[IPL_TTY];
/*
* Audio devices are not allowed to perform memory allocation
* in their interrupt routines, and they have fairly "real-time"
* requirements, so give them a high interrupt priority.
*/
sa11x0_imask[IPL_AUDIO] &= sa11x0_imask[IPL_VM];
/*
* splclock() must block anything that uses the scheduler.
*/
sa11x0_imask[IPL_CLOCK] &= sa11x0_imask[IPL_AUDIO];
/*
* splhigh() must block "everything".
*/
sa11x0_imask[IPL_HIGH] &= sa11x0_imask[IPL_STATCLOCK];
/*
* XXX We need serial drivers to run at the absolute highest priority
* in order to avoid overruns, so serial > high.
*/
sa11x0_imask[IPL_TTY] &= sa11x0_imask[IPL_HIGH];
#ifdef DEBUG
for (level = IPL_NONE; level < NIPL; level++) {
printf("imask %d, %x\n", level, sa11x0_imask[level]);
}
#endif
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
for (irq = 0; irq < ICU_LEN; irq++) {
int max_irq = IPL_NONE;
TAILQ_FOREACH(ih, &handler[irq].list, ih_list) {
if (ih->ih_level > max_irq)
max_irq = ih->ih_level;
}
extirq_level[irq] = max_irq;
}
#endif
write_icu(SAIPIC_MR, sa11x0_imask[current_spl_level]);
restore_interrupts(psw);
}
void
sa11x0_init_interrupt_masks(void)
{
memset(sa11x0_imask, 0, sizeof(sa11x0_imask));
/*
* IPL_NONE has soft interrupts enabled only, at least until
* hardware handlers are installed.
*/
sa11x0_imask[IPL_NONE] =
SI_TO_IRQBIT(SI_SOFT) |
SI_TO_IRQBIT(SI_SOFTCLOCK) |
SI_TO_IRQBIT(SI_SOFTNET) |
SI_TO_IRQBIT(SI_SOFTSERIAL);
/*
* Initialize the soft interrupt masks to block themselves.
*/
sa11x0_imask[IPL_SOFT] = ~SI_TO_IRQBIT(SI_SOFT);
sa11x0_imask[IPL_SOFTCLOCK] = ~SI_TO_IRQBIT(SI_SOFTCLOCK);
sa11x0_imask[IPL_SOFTNET] = ~SI_TO_IRQBIT(SI_SOFTNET);
sa11x0_imask[IPL_SOFTSERIAL] = ~SI_TO_IRQBIT(SI_SOFTSERIAL);
sa11x0_imask[IPL_SOFT] &= sa11x0_imask[IPL_NONE];
/*
* splsoftclock() is the only interface that users of the
* generic software interrupt facility have to block their
* soft intrs, so splsoftclock() must also block IPL_SOFT.
*/
sa11x0_imask[IPL_SOFTCLOCK] &= sa11x0_imask[IPL_SOFT];
/*
* splsoftnet() must also block splsoftclock(), since we don't
* want timer-driven network events to occur while we're
* processing incoming packets.
*/
sa11x0_imask[IPL_SOFTNET] &= sa11x0_imask[IPL_SOFTCLOCK];
}
void
sa11x0_do_pending(void)
{
static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
int oldirqstate, spl_save;
if (__cpu_simple_lock_try(&processing) == 0)
return;
spl_save = current_spl_level;
oldirqstate = disable_interrupts(I32_bit);
#if 1
#define DO_SOFTINT(si,ipl) \
if ((softint_pending & sa11x0_imask[current_spl_level]) & \
SI_TO_IRQBIT(si)) { \
softint_pending &= ~SI_TO_IRQBIT(si); \
if (current_spl_level < ipl) \
sa11x0_setipl(ipl); \
restore_interrupts(oldirqstate); \
softintr_dispatch(si); \
oldirqstate = disable_interrupts(I32_bit); \
sa11x0_setipl(spl_save); \
}
do {
DO_SOFTINT(SI_SOFTSERIAL,IPL_SOFTSERIAL);
DO_SOFTINT(SI_SOFTNET, IPL_SOFTNET);
DO_SOFTINT(SI_SOFTCLOCK, IPL_SOFTCLOCK);
DO_SOFTINT(SI_SOFT, IPL_SOFT);
} while( softint_pending & sa11x0_imask[current_spl_level] );
#else
while( (si = find_first_bit(softint_pending & sa11x0_imask[current_spl_level])) >= 0 ){
softint_pending &= ~SI_TO_IRQBIT(si);
if (current_spl_level < ipl)
sa11x0_setipl(ipl);
restore_interrupts(oldirqstate);
softintr_dispatch(si);
oldirqstate = disable_interrupts(I32_bit);
sa11x0_setipl(spl_save);
}
#endif
__cpu_simple_unlock(&processing);
restore_interrupts(oldirqstate);
}
#undef splx
void
splx(int ipl)
{
sa11x0_splx(ipl);
}
#undef _splraise
int
_splraise(int ipl)
{
return sa11x0_splraise(ipl);
}
#undef _spllower
int
_spllower(int ipl)
{
return sa11x0_spllower(ipl);
}
#undef _setsoftintr
void
_setsoftintr(int si)
{
return sa11x0_setsoftintr(si);
}
void *
_sa11x0_intr_establish(int irqno, int level,
int (*func)(void *), void *arg, char *name)
{
int psw;
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
struct intrhand *ih;
#else
struct intrhandler *ih;
#endif
if (irqno < 0 || irqno >= ICU_LEN - 1)
panic("intr_establish: bogus irq number %d", irqno);
psw = disable_interrupts(I32_bit);
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
/* no point in sleeping unless someone can free memory. */
MALLOC(ih, struct intrhand *, sizeof *ih, M_DEVBUF,
cold ? M_NOWAIT : M_WAITOK);
if (ih == NULL)
panic("intr_establish: can't malloc handler info");
ih->ih_func = func;
ih->ih_arg = arg;
ih->ih_level = level;
ih->ih_irq = irqno;
TAILQ_INSERT_TAIL(&handler[irqno].list, ih, ih_list);
#else
ih = &handler[irqno];
ih->arg = arg;
ih->func = func;
ih->name = name;
ih->ih_irq = irqno;
extirq_level[irqno] = level;
#endif
if (name != NULL)
evcount_attach(&ih->ih_count, name, (void *)&ih->ih_irq,
&evcount_intr);
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
sa11x0_update_intr_masks();
#else
sa11x0_update_intr_masks(irqno, level);
#endif
restore_interrupts(psw);
return (ih);
}
void
sa11x0_intr_disestablish(void *cookie)
{
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
int psw;
struct intrhand *ih = cookie;
int irqno = ih->ih_irq;
psw = disable_interrupts(I32_bit);
TAILQ_REMOVE(&handler[irqno].list, ih, ih_list);
FREE(ih, M_DEVBUF);
sa11x0_update_intr_masks();
restore_interrupts(psw);
#else
struct intrhandler *lhandler = cookie;
int irqno;
int psw;
struct intrhandler *ih;
irqno = lhandler - handler;
if (irqno < 1 || irqno >= ICU_LEN)
panic("intr_disestablish: bogus irq number %d", irqno);
psw = disable_interrupts(I32_bit);
ih = &handler[irqno];
if (ih->name != NULL)
evcount_detach(&ih->ih_count);
ih->arg = (void *) irqno;
ih->func = sa11x0_stray_interrupt;
ih->name = "stray";
extirq_level[irqno] = IPL_SERIAL;
sa11x0_update_intr_masks(irqno, IPL_SERIAL);
restore_interrupts(psw);
#endif
}
/*
* Glue for drivers of sa11x0 compatible integrated logic.
*/
void *
sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level,
int (*ih_fun)(void *), void *ih_arg, char *name)
{
/* XXX */
return _sa11x0_intr_establish(irq, level, ih_fun, ih_arg, name);
}
void
sa11x0_setipl(int new)
{
u_int32_t intr_mask;
intr_mask = sa11x0_imask[new];
current_spl_level = new;
write_icu( SAIPIC_MR, intr_mask );
}
void
sa11x0_splx(int new)
{
int psw;
psw = disable_interrupts(I32_bit);
sa11x0_setipl(new);
restore_interrupts(psw);
/* If there are pending software interrupts, process them. */
if (softint_pending & sa11x0_imask[current_spl_level])
sa11x0_do_pending();
}
int
sa11x0_splraise(int ipl)
{
int old, psw;
old = current_spl_level;
if( ipl > current_spl_level ){
psw = disable_interrupts(I32_bit);
sa11x0_setipl(ipl);
restore_interrupts(psw);
}
return (old);
}
int
sa11x0_spllower(int ipl)
{
int old = current_spl_level;
int psw = disable_interrupts(I32_bit);
sa11x0_splx(ipl);
restore_interrupts(psw);
return(old);
}
void
sa11x0_setsoftintr(int si)
{
#if 0
atomic_set_bit( (u_int *)&softint_pending, SI_TO_IRQBIT(si) );
#else
softint_pending |= SI_TO_IRQBIT(si);
#endif
/* Process unmasked pending soft interrupts. */
if ( softint_pending & sa11x0_imask[current_spl_level] )
sa11x0_do_pending();
}
const char *
sa11x0_intr_string(void *cookie)
{
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
struct intrhand *ih = cookie;
#else
struct intrhandler *lhandler = cookie;
#endif
static char irqstr[32];
if (ih == NULL)
snprintf(irqstr, sizeof irqstr, "couldn't establish interrupt");
else
snprintf(irqstr, sizeof irqstr, "irq %ld", ih->ih_irq);
return irqstr;
}
#ifdef DIAGNOSTIC
void
sa11x0_splassert_check(int wantipl, const char *func)
{
int oldipl = current_spl_level, psw;
if (oldipl < wantipl) {
splassert_fail(wantipl, oldipl, func);
/*
* If the splassert_ctl is set to not panic, raise the ipl
* in a feeble attempt to reduce damage.
*/
psw = disable_interrupts(I32_bit);
sa11x0_setipl(wantipl);
restore_interrupts(psw);
}
}
#endif