Return to sa11x0_comreg.h CVS log

Up to [local] / sys / arch / arm / sa11x0

Annotation of sys/arch/arm/sa11x0/sa11x0_comreg.h, Revision 1.1

1.1     ! nbrk        1: /*      $NetBSD: sa11x0_comreg.h,v 1.2 2006/04/11 15:24:24 peter Exp $        */
        !             2:
        !             3: /*-
        !             4:  * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
        !             5:  *
        !             6:  * This code is derived from software contributed to The NetBSD Foundation
        !             7:  * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
        !             8:  *
        !             9:  * Redistribution and use in source and binary forms, with or without
        !            10:  * modification, are permitted provided that the following conditions
        !            11:  * are met:
        !            12:  * 1. Redistributions of source code must retain the above copyright
        !            13:  *    notice, this list of conditions and the following disclaimer.
        !            14:  * 2. Redistributions in binary form must reproduce the above copyright
        !            15:  *    notice, this list of conditions and the following disclaimer in the
        !            16:  *    documentation and/or other materials provided with the distribution.
        !            17:  * 3. All advertising materials mentioning features or use of this software
        !            18:  *    must display the following acknowledgement:
        !            19:  *      This product includes software developed by the NetBSD
        !            20:  *      Foundation, Inc. and its contributors.
        !            21:  * 4. Neither the name of The NetBSD Foundation nor the names of its
        !            22:  *    contributors may be used to endorse or promote products derived
        !            23:  *    from this software without specific prior written permission.
        !            24:  *
        !            25:  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
        !            26:  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
        !            27:  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
        !            28:  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
        !            29:  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
        !            30:  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
        !            31:  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
        !            32:  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
        !            33:  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
        !            34:  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
        !            35:  * POSSIBILITY OF SUCH DAMAGE.
        !            36:  */
        !            37:
        !            38: /* SA11[01]0 integrated UART interface */
        !            39:
        !            40: /* #define SACOM_BASE  0x80050000 */
        !            41:
        !            42: #define SACOM_FREQ     (3686400 / 16)
        !            43: #define SACOMSPEED(b)  (SACOM_FREQ / (b) - 1)
        !            44:
        !            45: /* size of I/O space */
        !            46: #define SACOM_NPORTS   9
        !            47:
        !            48: #define SACOM_TXFIFOLEN                8
        !            49: #define SACOM_RXFIFOLEN                12
        !            50:
        !            51: /* UART control register 0 */
        !            52: #define SACOM_CR0      0x00
        !            53: #define CR0_PE         0x01    /* Parity enable */
        !            54: #define CR0_OES                0x02    /* Odd/even parity select */
        !            55: #define CR0_SBS                0x04    /* Stop bit select */
        !            56: #define CR0_DSS                0x08    /* Data size select */
        !            57: #define CR0_SCE                0x10    /* Sample clock enable */
        !            58: #define CR0_RCE                0x20    /* Receive clock edge enable */
        !            59: #define CR0_TCE                0x40    /* Transmit clock edge enable */
        !            60:
        !            61: /* UART control register 1 and 2 - baud rate divisor */
        !            62: #define SACOM_CR1      0x04
        !            63: #define SACOM_CR2      0x08
        !            64:
        !            65: /* UART control register 3 */
        !            66: #define SACOM_CR3      0x0C
        !            67: #define CR3_RXE                0x01    /* Receiver enable */
        !            68: #define CR3_TXE                0x02    /* Transmitter enable */
        !            69: #define CR3_BRK                0x04    /* Break */
        !            70: #define CR3_RIE                0x08    /* Receive FIFO interrupt enable */
        !            71: #define CR3_TIE                0x10    /* Transmit FIFO interrupt enable */
        !            72: #define CR3_LBM                0x20    /* Loopback mode */
        !            73:
        !            74: /* UART data register */
        !            75: #define SACOM_DR       0x14
        !            76: #define DR_PRE         0x100   /* Parity error */
        !            77: #define DR_FRE         0x200   /* Framing error */
        !            78: #define DR_ROR         0x400   /* Receiver overrun */
        !            79:
        !            80: /* UART status register 0 */
        !            81: #define SACOM_SR0      0x1C
        !            82: #define SR0_TFS                0x01    /* Transmit FIFO service request */
        !            83: #define SR0_RFS                0x02    /* Receive FIFO service request */
        !            84: #define SR0_RID                0x04    /* Receiver idle */
        !            85: #define SR0_RBB                0x08    /* Receiver begin of break */
        !            86: #define SR0_REB                0x10    /* Receiver end of break */
        !            87: #define SR0_EIF                0x20    /* Error in FIFO */
        !            88:
        !            89: /* UART status register 1 */
        !            90: #define SACOM_SR1      0x20
        !            91: #define SR1_TBY                0x01    /* Transmitter busy */
        !            92: #define SR1_RNE                0x02    /* Receive FIFO not empty */
        !            93: #define SR1_TNF                0x04    /* Transmit FIFO not full */
        !            94: #define SR1_PRE                0x08    /* Parity error */
        !            95: #define SR1_FRE                0x10    /* Framing error */
        !            96: #define SR1_ROR                0x20    /* Receive FIFO overrun */