Annotation of sys/arch/arm/s3c2xx0/sscom_var.h, Revision 1.1.1.1
1.1 nbrk 1: /* $NetBSD: sscom_var.h,v 1.7 2006/03/06 20:21:25 rjs Exp $ */
2:
3: /*
4: * Copyright (c) 2002, 2003 Fujitsu Component Limited
5: * Copyright (c) 2002, 2003 Genetec Corporation
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. Neither the name of The Fujitsu Component Limited nor the name of
17: * Genetec corporation may not be used to endorse or promote products
18: * derived from this software without specific prior written permission.
19: *
20: * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
21: * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
22: * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23: * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24: * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
25: * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26: * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27: * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28: * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29: * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30: * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31: * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32: * SUCH DAMAGE.
33: */
34: /* derived from sys/dev/ic/comvar.h */
35:
36: /*
37: * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
38: *
39: * Redistribution and use in source and binary forms, with or without
40: * modification, are permitted provided that the following conditions
41: * are met:
42: * 1. Redistributions of source code must retain the above copyright
43: * notice, this list of conditions and the following disclaimer.
44: * 2. Redistributions in binary form must reproduce the above copyright
45: * notice, this list of conditions and the following disclaimer in the
46: * documentation and/or other materials provided with the distribution.
47: * 3. All advertising materials mentioning features or use of this software
48: * must display the following acknowledgement:
49: * This product includes software developed by Christopher G. Demetriou
50: * for the NetBSD Project.
51: * 4. The name of the author may not be used to endorse or promote products
52: * derived from this software without specific prior written permission
53: *
54: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
55: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
56: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
57: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
58: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
59: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
63: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64: */
65:
66: #ifndef _ARM_S3C2XX0_SSCOM_VAR_H
67: #define _ARM_S3C2XX0_SSCOM_VAR_H
68:
69: #include "opt_multiprocessor.h"
70: #include "opt_lockdebug.h"
71: #include "opt_sscom.h"
72:
73: #include <sys/param.h>
74: #include <sys/systm.h>
75: #include <sys/device.h>
76: #include <sys/termios.h>
77: #include <sys/callout.h>
78: #include <machine/bus.h>
79:
80: #ifdef SSCOM_S3C2410
81: #include <arm/s3c2xx0/s3c2410reg.h>
82: #include <arm/s3c2xx0/s3c2410var.h>
83: #endif
84:
85: /* Hardware flag masks */
86: #define SSCOM_HW_FLOW 0x02
87: #define SSCOM_HW_DEV_OK 0x04
88: #define SSCOM_HW_CONSOLE 0x08
89: #define SSCOM_HW_KGDB 0x10
90: #define SSCOM_HW_TXINT 0x20
91: #define SSCOM_HW_RXINT 0x40
92:
93: /* Buffer size for character buffer */
94: #define SSCOM_RING_SIZE 2048
95:
96: struct sscom_softc {
97: struct device sc_dev;
98: void *sc_si;
99: struct tty *sc_tty;
100:
101: struct callout sc_diag_callout;
102:
103: int sc_unit; /* UART0/UART1 */
104: int sc_frequency;
105:
106: bus_space_tag_t sc_iot;
107: bus_space_handle_t sc_ioh;
108:
109: u_int sc_overflows,
110: sc_floods,
111: sc_errors;
112:
113: int sc_hwflags,
114: sc_swflags;
115:
116: u_int sc_r_hiwat,
117: sc_r_lowat;
118: u_char *volatile sc_rbget,
119: *volatile sc_rbput;
120: volatile u_int sc_rbavail;
121: u_char *sc_rbuf,
122: *sc_ebuf;
123:
124: u_char *sc_tba;
125: u_int sc_tbc,
126: sc_heldtbc;
127:
128: volatile u_char sc_rx_flags,
129: #define RX_TTY_BLOCKED 0x01
130: #define RX_TTY_OVERFLOWED 0x02
131: #define RX_IBUF_BLOCKED 0x04
132: #define RX_IBUF_OVERFLOWED 0x08
133: #define RX_ANY_BLOCK 0x0f
134: sc_tx_busy,
135: sc_tx_done,
136: sc_tx_stopped,
137: sc_st_check,
138: sc_rx_ready;
139:
140: /* data to stored in UART registers.
141: actual write to UART register is pended while sc_tx_busy */
142: uint16_t sc_ucon; /* control register */
143: uint16_t sc_ubrdiv; /* baudrate register */
144: uint8_t sc_heldchange; /* register changes are pended */
145: uint8_t sc_ulcon; /* line control */
146: uint8_t sc_umcon; /* modem control */
147: #define UMCON_HW_MASK (UMCON_RTS)
148: #define UMCON_DTR (1<<4) /* provided by other means such as GPIO */
149: uint8_t sc_msts; /* modem status */
150: #define MSTS_CTS UMSTAT_CTS /* bit0 */
151: #define MSTS_DCD (1<<1)
152: #define MSTS_DSR (1<<2)
153:
154: uint8_t sc_msr_dcd; /* DCD or 0 */
155: uint8_t sc_mcr_dtr; /* DTR or 0 or DTR|RTS*/
156: uint8_t sc_mcr_rts; /* RTS or DTR in sc_umcon */
157: uint8_t sc_msr_cts; /* CTS or DCD in sc_msts */
158:
159: uint8_t sc_msr_mask; /* sc_msr_cts|sc_msr_dcd */
160: uint8_t sc_mcr_active;
161: uint8_t sc_msr_delta;
162:
163: uint8_t sc_rx_irqno, sc_tx_irqno;
164:
165: #if 0
166: /* PPS signal on DCD, with or without inkernel clock disciplining */
167: u_char sc_ppsmask; /* pps signal mask */
168: u_char sc_ppsassert; /* pps leading edge */
169: u_char sc_ppsclear; /* pps trailing edge */
170: pps_info_t ppsinfo;
171: pps_params_t ppsparam;
172: #endif
173:
174: #if NRND > 0 && defined(RND_COM)
175: rndsource_element_t rnd_source;
176: #endif
177: #if (defined(MULTIPROCESSOR) || defined(LOCKDEBUG)) && defined(SSCOM_MPLOCK)
178: struct simplelock sc_lock;
179: #endif
180:
181: /*
182: * S3C2XX0's UART doesn't have modem control/status pins.
183: * On platforms with S3C2XX0, those pins are simply unavailable
184: * or provided by other means such as GPIO. Platform specific attach routine
185: * have to provide functions to read/write modem control/status pins.
186: */
187: int (* read_modem_status)( struct sscom_softc * );
188: void (* set_modem_control)( struct sscom_softc * );
189: };
190:
191: /* UART register address, etc. */
192: struct sscom_uart_info {
193: int unit;
194: char tx_int, rx_int, err_int;
195: bus_addr_t iobase;
196: };
197:
198: #define sscom_rxrdy(iot,ioh) \
199: (bus_space_read_1((iot), (ioh), SSCOM_UTRSTAT) & UTRSTAT_RXREADY)
200: #define sscom_getc(iot,ioh) bus_space_read_1((iot), (ioh), SSCOM_URXH)
201: #define sscom_geterr(iot,ioh) bus_space_read_1((iot), (ioh), SSCOM_UERSTAT)
202:
203: /*
204: * we need to tweak interrupt controller to mask/unmask rxint and/or txint.
205: */
206: #ifdef SSCOM_S3C2410
207: /* RXINTn, TXINTn and ERRn interrupts are cascaded to UARTn irq. */
208:
209: #define _sscom_intbit(irqno) (1<<((irqno)-S3C2410_SUBIRQ_MIN))
210:
211: #define sscom_unmask_rxint(sc) \
212: s3c2410_unmask_subinterrupts(_sscom_intbit((sc)->sc_rx_irqno))
213: #define sscom_mask_rxint(sc) \
214: s3c2410_mask_subinterrupts(_sscom_intbit((sc)->sc_rx_irqno))
215: #define sscom_unmask_txint(sc) \
216: s3c2410_unmask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno))
217: #define sscom_mask_txint(sc) \
218: s3c2410_mask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno))
219: #define sscom_unmask_txrxint(sc) \
220: s3c2410_unmask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno) | \
221: _sscom_intbit((sc)->sc_rx_irqno))
222: #define sscom_mask_txrxint(sc) \
223: s3c2410_mask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno) | \
224: _sscom_intbit((sc)->sc_rx_irqno))
225:
226: #else
227:
228: /* for S3C2800 and S3C2400 */
229: #define sscom_unmask_rxint(sc) s3c2xx0_unmask_interrupts(1<<(sc)->sc_rx_irqno)
230: #define sscom_mask_rxint(sc) s3c2xx0_mask_interrupts(1<<(sc)->sc_rx_irqno)
231: #define sscom_unmask_txint(sc) s3c2xx0_unmask_interrupts(1<<(sc)->sc_tx_irqno)
232: #define sscom_mask_txint(sc) s3c2xx0_mask_interrupts(1<<(sc)->sc_tx_irqno)
233: #define sscom_unmask_txrxint(sc) \
234: s3c2xx0_unmask_interrupts((1<<(sc)->sc_tx_irqno)|(1<<(sc)->sc_rx_irqno))
235: #define sscom_mask_txrxint(sc) \
236: s3c2xx0_mask_interrupts((1<<(sc)->sc_tx_irqno)|(1<<(sc)->sc_rx_irqno))
237:
238: #endif /* SSCOM_S3C2410 */
239:
240: #define sscom_enable_rxint(sc) \
241: (sscom_unmask_rxint(sc), ((sc)->sc_hwflags |= SSCOM_HW_RXINT))
242: #define sscom_disable_rxint(sc) \
243: (sscom_mask_rxint(sc), ((sc)->sc_hwflags &= ~SSCOM_HW_RXINT))
244: #define sscom_enable_txint(sc) \
245: (sscom_unmask_txint(sc), ((sc)->sc_hwflags |= SSCOM_HW_TXINT))
246: #define sscom_disable_txint(sc) \
247: (sscom_mask_txint(sc),((sc)->sc_hwflags &= ~SSCOM_HW_TXINT))
248: #define sscom_enable_txrxint(sc) \
249: (sscom_unmask_txrxint(sc),((sc)->sc_hwflags |= (SSCOM_HW_TXINT|SSCOM_HW_RXINT)))
250: #define sscom_disable_txrxint(sc) \
251: (sscom_mask_txrxint(sc),((sc)->sc_hwflags &= ~(SSCOM_HW_TXINT|SSCOM_HW_RXINT)))
252:
253:
254: int sscomspeed(long, long);
255: void sscom_attach_subr(struct sscom_softc *);
256:
257: int sscom_detach(struct device *, int);
258: int sscom_activate(struct device *, enum devact);
259: void sscom_shutdown(struct sscom_softc *);
260: void sscomdiag (void *);
261: void sscomstart(struct tty *);
262: int sscomparam(struct tty *, struct termios *);
263: int sscomread(dev_t, struct uio *, int);
264: void sscom_config(struct sscom_softc *);
265:
266: int sscomtxintr(void *);
267: int sscomrxintr(void *);
268:
269: int sscom_cnattach(bus_space_tag_t, const struct sscom_uart_info *,
270: int, int, tcflag_t);
271: void sscom_cndetach(void);
272: int sscom_is_console(bus_space_tag_t, int, bus_space_handle_t *);
273:
274: #ifdef KGDB
275: int sscom_kgdb_attach(bus_space_tag_t, const struct sscom_uart_info *,
276: int, int, tcflag_t);
277: #endif
278:
279: #endif /* _ARM_S3C2XX0_SSCOM_VAR_H */
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