Annotation of sys/arch/arm/s3c2xx0/s3c2xx0_intr.h, Revision 1.1
1.1 ! nbrk 1: /* $NetBSD: s3c2xx0_intr.h,v 1.10 2005/12/24 20:06:52 perry Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 2002, 2003 Fujitsu Component Limited
! 5: * Copyright (c) 2002, 2003 Genetec Corporation
! 6: * All rights reserved.
! 7: *
! 8: * Redistribution and use in source and binary forms, with or without
! 9: * modification, are permitted provided that the following conditions
! 10: * are met:
! 11: * 1. Redistributions of source code must retain the above copyright
! 12: * notice, this list of conditions and the following disclaimer.
! 13: * 2. Redistributions in binary form must reproduce the above copyright
! 14: * notice, this list of conditions and the following disclaimer in the
! 15: * documentation and/or other materials provided with the distribution.
! 16: * 3. Neither the name of The Fujitsu Component Limited nor the name of
! 17: * Genetec corporation may not be used to endorse or promote products
! 18: * derived from this software without specific prior written permission.
! 19: *
! 20: * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
! 21: * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
! 22: * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
! 23: * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
! 24: * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
! 25: * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
! 26: * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
! 27: * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
! 28: * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! 29: * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
! 30: * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
! 31: * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 32: * SUCH DAMAGE.
! 33: */
! 34:
! 35: /* Derived from i80321_intr.h */
! 36:
! 37: /*
! 38: * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
! 39: * All rights reserved.
! 40: *
! 41: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
! 42: *
! 43: * Redistribution and use in source and binary forms, with or without
! 44: * modification, are permitted provided that the following conditions
! 45: * are met:
! 46: * 1. Redistributions of source code must retain the above copyright
! 47: * notice, this list of conditions and the following disclaimer.
! 48: * 2. Redistributions in binary form must reproduce the above copyright
! 49: * notice, this list of conditions and the following disclaimer in the
! 50: * documentation and/or other materials provided with the distribution.
! 51: * 3. All advertising materials mentioning features or use of this software
! 52: * must display the following acknowledgement:
! 53: * This product includes software developed for the NetBSD Project by
! 54: * Wasabi Systems, Inc.
! 55: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
! 56: * or promote products derived from this software without specific prior
! 57: * written permission.
! 58: *
! 59: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
! 60: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 61: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 62: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
! 63: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 64: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 65: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 66: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 67: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 68: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 69: * POSSIBILITY OF SUCH DAMAGE.
! 70: */
! 71:
! 72: #ifndef _S3C2XX0_INTR_H_
! 73: #define _S3C2XX0_INTR_H_
! 74:
! 75: #include <arm/cpu.h>
! 76: #include <arm/armreg.h>
! 77: #include <arm/cpufunc.h>
! 78: #include <machine/atomic.h>
! 79: #include <machine/intr.h>
! 80: #include <arm/softintr.h>
! 81:
! 82: #include <arm/s3c2xx0/s3c2xx0reg.h>
! 83:
! 84: typedef int (* s3c2xx0_irq_handler_t)(void *);
! 85:
! 86: extern volatile uint32_t *s3c2xx0_intr_mask_reg;
! 87:
! 88: extern volatile int current_spl_level;
! 89: extern volatile int intr_mask;
! 90: extern volatile int global_intr_mask;
! 91: extern volatile int softint_pending;
! 92: extern int s3c2xx0_imask[];
! 93: extern int s3c2xx0_ilevel[];
! 94:
! 95: void s3c2xx0_do_pending(int);
! 96: void s3c2xx0_update_intr_masks( int, int );
! 97:
! 98: static inline void
! 99: s3c2xx0_mask_interrupts(int mask)
! 100: {
! 101: int save = disable_interrupts(I32_bit);
! 102: global_intr_mask &= ~mask;
! 103: s3c2xx0_update_hw_mask();
! 104: restore_interrupts(save);
! 105: }
! 106:
! 107: static inline void
! 108: s3c2xx0_unmask_interrupts(int mask)
! 109: {
! 110: int save = disable_interrupts(I32_bit);
! 111: global_intr_mask |= mask;
! 112: s3c2xx0_update_hw_mask();
! 113: restore_interrupts(save);
! 114: }
! 115:
! 116: static inline void
! 117: s3c2xx0_setipl(int new)
! 118: {
! 119: current_spl_level = new;
! 120: intr_mask = s3c2xx0_imask[current_spl_level];
! 121: s3c2xx0_update_hw_mask();
! 122: update_softintr_mask();
! 123: }
! 124:
! 125:
! 126: static inline void
! 127: s3c2xx0_splx(int new)
! 128: {
! 129: int psw;
! 130:
! 131: psw = disable_interrupts(I32_bit);
! 132: s3c2xx0_setipl(new);
! 133: restore_interrupts(psw);
! 134:
! 135: /* If there are software interrupts to process, do it. */
! 136: if (get_pending_softint())
! 137: s3c2xx0_do_pending(0);
! 138: }
! 139:
! 140:
! 141: static inline int
! 142: s3c2xx0_splraise(int ipl)
! 143: {
! 144: int old, psw;
! 145:
! 146: old = current_spl_level;
! 147: if( ipl > current_spl_level ){
! 148: psw = disable_interrupts(I32_bit);
! 149: s3c2xx0_setipl(ipl);
! 150: restore_interrupts(psw);
! 151: }
! 152:
! 153: return (old);
! 154: }
! 155:
! 156: static inline int
! 157: s3c2xx0_spllower(int ipl)
! 158: {
! 159: int old = current_spl_level;
! 160: int psw = disable_interrupts(I32_bit);
! 161: s3c2xx0_splx(ipl);
! 162: restore_interrupts(psw);
! 163: return(old);
! 164: }
! 165:
! 166: static inline void
! 167: s3c2xx0_setsoftintr(int si)
! 168: {
! 169:
! 170: atomic_set_bit( (u_int *)__UNVOLATILE(&softint_pending),
! 171: SI_TO_IRQBIT(si) );
! 172:
! 173: /* Process unmasked pending soft interrupts. */
! 174: if (get_pending_softint())
! 175: s3c2xx0_do_pending(0);
! 176:
! 177: }
! 178:
! 179:
! 180: int _splraise(int);
! 181: int _spllower(int);
! 182: void splx(int);
! 183: void _setsoftintr(int);
! 184:
! 185: #if !defined(EVBARM_SPL_NOINLINE)
! 186:
! 187: #define splx(new) s3c2xx0_splx(new)
! 188: #define _spllower(ipl) s3c2xx0_spllower(ipl)
! 189: #define _splraise(ipl) s3c2xx0_splraise(ipl)
! 190: #define _setsoftintr(si) s3c2xx0_setsoftintr(si)
! 191:
! 192: #endif /* !EVBARM_SPL_NOINTR */
! 193:
! 194:
! 195: /*
! 196: * interrupt dispatch table.
! 197: */
! 198: #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
! 199: struct intrhand {
! 200: TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
! 201: s3c2xx0_irq_handler_t ih_func; /* handler */
! 202: void *ih_arg; /* arg for handler */
! 203: };
! 204: #endif
! 205:
! 206: struct s3c2xx0_intr_dispatch {
! 207: #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
! 208: TAILQ_HEAD(,intrhand) list;
! 209: #else
! 210: s3c2xx0_irq_handler_t func;
! 211: #endif
! 212: void *cookie; /* NULL for stackframe */
! 213: int level;
! 214: /* struct evbnt ev; */
! 215: };
! 216:
! 217: /* used by s3c2{80,40,41}0 interrupt handler */
! 218: void s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch *, int );
! 219:
! 220: /* initialize some variable so that splfoo() doesn't touch ileegal
! 221: address during bootstrap */
! 222: void s3c2xx0_intr_bootstrap(vaddr_t);
! 223:
! 224: #endif /* _S3C2XX0_INTR_H_ */
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