Annotation of sys/arch/arm/s3c2xx0/s3c24x0reg.h, Revision 1.1
1.1 ! nbrk 1: /* $NetBSD: s3c24x0reg.h,v 1.8 2005/12/11 12:16:51 christos Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 2003 Genetec corporation All rights reserved.
! 5: * Written by Hiroyuki Bessho for Genetec corporation.
! 6: *
! 7: * Redistribution and use in source and binary forms, with or without
! 8: * modification, are permitted provided that the following conditions
! 9: * are met:
! 10: * 1. Redistributions of source code must retain the above copyright
! 11: * notice, this list of conditions and the following disclaimer.
! 12: * 2. Redistributions in binary form must reproduce the above copyright
! 13: * notice, this list of conditions and the following disclaimer in the
! 14: * documentation and/or other materials provided with the distribution.
! 15: * 3. The name of Genetec corporation may not be used to endorse
! 16: * or promote products derived from this software without specific prior
! 17: * written permission.
! 18: *
! 19: * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
! 20: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 21: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 22: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
! 23: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 24: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 25: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 26: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 27: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 28: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 29: * POSSIBILITY OF SUCH DAMAGE.
! 30: */
! 31:
! 32:
! 33: /*
! 34: * Samsung S3C2410X/2400 processor is ARM920T based integrated CPU
! 35: *
! 36: * Reference:
! 37: * S3C2410X User's Manual
! 38: * S3C2400 User's Manual
! 39: */
! 40: #ifndef _ARM_S3C2XX0_S3C24X0REG_H_
! 41: #define _ARM_S3C2XX0_S3C24X0REG_H_
! 42:
! 43: /* Memory controller */
! 44: #define MEMCTL_BWSCON 0x00 /* Bus width and wait status */
! 45: #define BWSCON_DW0_SHIFT 1 /* bank0 is odd */
! 46: #define BWSCON_BANK_SHIFT(n) (4*(n)) /* for bank 1..7 */
! 47: #define BWSCON_DW_MASK 0x03
! 48: #define BWSCON_DW_8 0
! 49: #define BWSCON_DW_16 1
! 50: #define BWSCON_DW_32 2
! 51: #define BWSCON_WS 0x04 /* WAIT enable for the bank */
! 52: #define BWSCON_ST 0x08 /* SRAM use UB/LB for the bank */
! 53:
! 54: #define MEMCTL_BANKCON0 0x04 /* Boot ROM control */
! 55: #define MEMCTL_BANKCON(n) (0x04+4*(n)) /* BANKn control */
! 56: #define BANKCON_MT_SHIFT 15
! 57: #define BANKCON_MT_ROM (0<<BANKCON_MT_SHIFT)
! 58: #define BANKCON_MT_DRAM (3<<BANKCON_MT_SHIFT)
! 59: #define BANKCON_TACS_SHIFT 13 /* address set-up time to nGCS */
! 60: #define BANKCON_TCOS_SHIFT 11 /* CS set-up to nOE */
! 61: #define BANKCON_TACC_SHIFT 8 /* CS set-up to nOE */
! 62: #define BANKCON_TOCH_SHIFT 6 /* CS hold time from OE */
! 63: #define BANKCON_TCAH_SHIFT 4 /* address hold time from OE */
! 64: #define BANKCON_TACP_SHIFT 2 /* page mode access cycle */
! 65: #define BANKCON_TACP_2 (0<<BANKCON_TACP_SHIFT)
! 66: #define BANKCON_TACP_3 (1<<BANKCON_TACP_SHIFT)
! 67: #define BANKCON_TACP_4 (2<<BANKCON_TACP_SHIFT)
! 68: #define BANKCON_TACP_6 (3<<BANKCON_TACP_SHIFT)
! 69: #define BANKCON_PMC_4 (1<<0)
! 70: #define BANKCON_PMC_8 (2<<0)
! 71: #define BANKCON_PMC_16 (3<<0)
! 72: #define BANKCON_TRCD_SHIFT 2 /* RAS to CAS delay */
! 73: #define BANKCON_TRCD_2 (0<<2)
! 74: #define BANKCON_TRCD_3 (1<<2)
! 75: #define BANKCON_TRCD_4 (2<<2)
! 76: #define BANKCON_SCAN_8 (0<<0) /* Column address number */
! 77: #define BANKCON_SCAN_9 (1<<0)
! 78: #define BANKCON_SCAN_10 (2<<0)
! 79: #define MEMCTL_REFRESH 0x24 /* DRAM?SDRAM Refresh */
! 80: #define REFRESH_REFEN (1<<23)
! 81: #define REFRESH_TREFMD (1<<22) /* 1=self refresh */
! 82: #define REFRESH_TRP_2 (0<<20)
! 83: #define REFRESH_TRP_3 (1<<20)
! 84: #define REFRESH_TRP_4 (2<<20)
! 85: #define REFRESH_TRC_4 (0<<18)
! 86: #define REFRESH_TRC_5 (1<<18)
! 87: #define REFRESH_TRC_6 (2<<18)
! 88: #define REFRESH_TRC_7 (3<<18)
! 89: #define REFRESH_COUNTER_MASK 0x3ff
! 90: #define MEMCTL_BANKSIZE 0x28 /* Flexible Bank size */
! 91: #define MEMCTL_MRSRB6 0x2c /* SDRAM Mode register */
! 92: #define MEMCTL_MRSRB7 0x30
! 93: #define MRSR_CL_SHIFT 4 /* CAS Latency */
! 94:
! 95: #define S3C24X0_MEMCTL_SIZE 0x34
! 96:
! 97: /* USB Host controller */
! 98: #define S3C24X0_USBHC_SIZE 0x5c
! 99:
! 100: /* Interrupt controller */
! 101: #define INTCTL_PRIORITY 0x0c /* IRQ Priority control */
! 102: #define INTCTL_INTPND 0x10 /* Interrupt request status */
! 103: #define INTCTL_INTOFFSET 0x14 /* Interrupt request source */
! 104:
! 105: /* Interrupt source */
! 106: #define S3C24X0_INT_ADCTC 31 /* ADC (and TC for 2410 */
! 107: #define S3C24X0_INT_RTC 30 /* RTC alarm */
! 108: #define S3C2400_INT_UTXD1 29 /* UART1 Tx INT (2400 only) */
! 109: #define S3C2410_INT_SPI1 29 /* SPI 1 (2410 only) */
! 110: #define S3C2400_INT_UTXD0 28 /* UART0 Tx INT (2400 only) */
! 111: #define S3C2410_INT_UART0 28 /* UART0 (2410 only) */
! 112: #define S3C24X0_INT_IIC 27
! 113: #define S3C24X0_INT_USBH 26 /* USB Host */
! 114: #define S3C24X0_INT_USBD 25 /* USB Device */
! 115: #define S3C2400_INT_URXD1 24 /* UART1 Rx INT (2400 only) */
! 116: #define S3C2400_INT_URXD0 23 /* UART0 Rx INT (2400 only) */
! 117: #define S3C2410_INT_UART1 23 /* UART0 (2410 only) */
! 118: #define S3C24X0_INT_SPI0 22 /* SPI 0 */
! 119: #define S3C2400_INT_MMC 21
! 120: #define S3C2410_INT_SDI 21
! 121: #define S3C24X0_INT_DMA3 20
! 122: #define S3C24X0_INT_DMA2 19
! 123: #define S3C24X0_INT_DMA1 18
! 124: #define S3C24X0_INT_DMA0 17
! 125: #define S3C2410_INT_LCD 16
! 126:
! 127: #define S3C2400_INT_UERR 15 /* UART 0/1 Error int (2400) */
! 128: #define S3C2410_INT_UART2 15 /* UART2 int (2410) */
! 129: #define S3C24X0_INT_TIMER4 14
! 130: #define S3C24X0_INT_TIMER3 13
! 131: #define S3C24X0_INT_TIMER2 12
! 132: #define S3C24X0_INT_TIMER1 11
! 133: #define S3C24X0_INT_TIMER0 10
! 134: #define S3C24X0_INT_TIMER(n) (10+(n)) /* timer interrupt [4:0] */
! 135: #define S3C24X0_INT_WDT 9 /* Watch dog timer */
! 136: #define S3C24X0_INT_TICK 8
! 137: #define S3C2410_INT_BFLT 7 /* Battery fault */
! 138: #define S3C2410_INT_8_23 5 /* Ext int 8..23 */
! 139: #define S3C2410_INT_4_7 4 /* Ext int 4..7 */
! 140: #define S3C24X0_INT_EXT(n) (n) /* External interrupt [7:0] for 2400,
! 141: * [3:0] for 2410 */
! 142: /* DMA controller */
! 143: /* XXX */
! 144:
! 145: /* Clock & power manager */
! 146: #define CLKMAN_LOCKTIME 0x00 /* PLL lock time */
! 147: #define CLKMAN_MPLLCON 0x04 /* MPLL control */
! 148: #define CLKMAN_UPLLCON 0x08 /* UPLL control */
! 149: #define PLLCON_MDIV_SHIFT 12
! 150: #define PLLCON_MDIV_MASK (0xff<<PLLCON_MDIV_SHIFT)
! 151: #define PLLCON_PDIV_SHIFT 4
! 152: #define PLLCON_PDIV_MASK (0x3f<<PLLCON_PDIV_SHIFT)
! 153: #define PLLCON_SDIV_SHIFT 0
! 154: #define PLLCON_SDIV_MASK (0x03<<PLLCON_SDIV_SHIFT)
! 155: #define CLKMAN_CLKCON 0x0c
! 156:
! 157: #define CLKMAN_CLKSLOW 0x10 /* slow clock controll */
! 158: #define CLKSLOW_UCLK (1<<7) /* 1=UPLL off */
! 159: #define CLKSLOW_MPLL (1<<5) /* 1=PLL off */
! 160: #define CLKSLOW_SLOW (1<<4) /* 1: Enable SLOW mode */
! 161: #define CLKSLOW_VAL_MASK 0x0f /* divider value for slow clock */
! 162:
! 163: #define CLKMAN_CLKDIVN 0x14 /* Software reset control */
! 164: #define CLKDIVN_HDIVN (1<<1)
! 165: #define CLKDIVN_PDIVN (1<<0)
! 166:
! 167: #define S3C24X0_CLKMAN_SIZE 0x18
! 168:
! 169: /* LCD controller */
! 170: #define LCDC_LCDCON1 0x00 /* control 1 */
! 171: #define LCDCON1_ENVID (1<<0) /* enable video */
! 172: #define LCDCON1_BPPMODE_SHIFT 1
! 173: #define LCDCON1_BPPMODE_MASK (0x0f<<LCDCON1_BPPMODE_SHIFT)
! 174: #define LCDCON1_BPPMODE_STN1 (0x0<<LCDCON1_BPPMODE_SHIFT)
! 175: #define LCDCON1_BPPMODE_STN2 (0x1<<LCDCON1_BPPMODE_SHIFT)
! 176: #define LCDCON1_BPPMODE_STN4 (0x2<<LCDCON1_BPPMODE_SHIFT)
! 177: #define LCDCON1_BPPMODE_STN8 (0x3<<LCDCON1_BPPMODE_SHIFT)
! 178: #define LCDCON1_BPPMODE_STN12 (0x4<<LCDCON1_BPPMODE_SHIFT)
! 179: #define LCDCON1_BPPMODE_TFT1 (0x8<<LCDCON1_BPPMODE_SHIFT)
! 180: #define LCDCON1_BPPMODE_TFT2 (0x9<<LCDCON1_BPPMODE_SHIFT)
! 181: #define LCDCON1_BPPMODE_TFT4 (0xa<<LCDCON1_BPPMODE_SHIFT)
! 182: #define LCDCON1_BPPMODE_TFT8 (0xb<<LCDCON1_BPPMODE_SHIFT)
! 183: #define LCDCON1_BPPMODE_TFT16 (0xc<<LCDCON1_BPPMODE_SHIFT)
! 184: #define LCDCON1_BPPMODE_TFT24 (0xd<<LCDCON1_BPPMODE_SHIFT)
! 185: #define LCDCON1_BPPMODE_TFTX (0x8<<LCDCON1_BPPMODE_SHIFT)
! 186:
! 187: #define LCDCON1_PNRMODE_SHIFT 5
! 188: #define LCDCON1_PNRMODE_MASK (0x3<<LCDCON1_PNRMODE_SHIFT)
! 189: #define LCDCON1_PNRMODE_DUALSTN4 (0x0<<LCDCON1_PNRMODE_SHIFT)
! 190: #define LCDCON1_PNRMODE_SINGLESTN4 (0x1<<LCDCON1_PNRMODE_SHIFT)
! 191: #define LCDCON1_PNRMODE_SINGLESTN8 (0x2<<LCDCON1_PNRMODE_SHIFT)
! 192: #define LCDCON1_PNRMODE_TFT (0x3<<LCDCON1_PNRMODE_SHIFT)
! 193:
! 194: #define LCDCON1_MMODE (1<<7) /* VM toggle rate */
! 195: #define LCDCON1_CLKVAL_SHIFT 8
! 196: #define LCDCON1_CLKVAL_MASK (0x3ff<<LCDCON1_CLKVAL_SHIFT)
! 197: #define LCDCON1_LINCNT_SHIFT 18
! 198: #define LCDCON1_LINCNT_MASK (0x3ff<<LCDCON1_LINCNT_SHIFT)
! 199:
! 200: #define LCDC_LCDCON2 0x04 /* control 2 */
! 201: #define LCDCON2_VPSW_SHIFT 0 /* TFT Vsync pulse width */
! 202: #define LCDCON2_VPSW_MASK (0x3f<<LCDCON2_VPSW_SHIFT)
! 203: #define LCDCON2_VFPD_SHIFT 6 /* TFT V front porch */
! 204: #define LCDCON2_VFPD_MASK (0xff<<LCDCON2_VFPD_SHIFT)
! 205: #define LCDCON2_LINEVAL_SHIFT 14 /* Vertical size */
! 206: #define LCDCON2_LINEVAL_MASK (0x3ff<<LCDCON2_LINEVAL_SHIFT)
! 207: #define LCDCON2_VBPD_SHIFT 24 /* TFT V back porch */
! 208: #define LCDCON2_VBPD_MASK (0xff<<LCDCON2_VBPD_SHIFT)
! 209:
! 210: #define LCDC_LCDCON3 0x08 /* control 2 */
! 211: #define LCDCON3_HFPD_SHIFT 0 /* TFT H front porch */
! 212: #define LCDCON3_HFPD_MASK (0xff<<LCDCON3_VPFD_SHIFT)
! 213: #define LCDCON3_LINEBLANK_SHIFT 0 /* STN H blank time */
! 214: #define LCDCON3_LINEBLANK_MASK (0xff<<LCDCON3_LINEBLANK_SHIFT)
! 215: #define LCDCON3_HOZVAL_SHIFT 8 /* Horizontal size */
! 216: #define LCDCON3_HOZVAL_MASK (0x7ff<<LCDCON3_HOZVAL_SHIFT)
! 217: #define LCDCON3_HBPD_SHIFT 19 /* TFT H back porch */
! 218: #define LCDCON3_HBPD_MASK (0x7f<<LCDCON3_HPBD_SHIFT)
! 219: #define LCDCON3_WDLY_SHIFT 19 /* STN vline delay */
! 220: #define LCDCON3_WDLY_MASK (0x03<<LCDCON3_WDLY_SHIFT)
! 221: #define LCDCON3_WDLY_16 (0x00<<LCDCON3_WDLY_SHIFT)
! 222: #define LCDCON3_WDLY_32 (0x01<<LCDCON3_WDLY_SHIFT)
! 223: #define LCDCON3_WDLY_64 (0x02<<LCDCON3_WDLY_SHIFT)
! 224: #define LCDCON3_WDLY_128 (0x03<<LCDCON3_WDLY_SHIFT)
! 225:
! 226: #define LCDC_LCDCON4 0x0c /* control 4 */
! 227: #define LCDCON4_HPSW_SHIFT 0 /* TFT Hsync pulse width */
! 228: #define LCDCON4_HPSW_MASK (0xff<<LCDCON4_HPSW_SHIFT)
! 229: #define LCDCON4_WLH_SHIFT 0 /* STN VLINE high width */
! 230: #define LCDCON4_WLH_MASK (0x03<<LCDCON4_WLH_SHIFT)
! 231: #define LCDCON4_WLH_16 (0x00<<LCDCON4_WLH_SHIFT)
! 232: #define LCDCON4_WLH_32 (0x01<<LCDCON4_WLH_SHIFT)
! 233: #define LCDCON4_WLH_64 (0x02<<LCDCON4_WLH_SHIFT)
! 234: #define LCDCON4_WLH_128 (0x03<<LCDCON4_WLH_SHIFT)
! 235:
! 236: #define LCDCON4_MVAL_SHIFT 8 /* STN VM toggle rate */
! 237: #define LCDCON4_MVAL_MASK (0xff<<LCDCON4_MVAL_SHIFT)
! 238:
! 239: #define LCDC_LCDCON5 0x10 /* control 5 */
! 240: #define LCDCON5_HWSWP (1<<0) /* half-word swap */
! 241: #define LCDCON5_BSWP (1<<1) /* byte swap */
! 242: #define LCDCON5_ENLEND (1<<2) /* TFT: enable LEND signal */
! 243: #define LCDCON5_PWREN (1<<3) /* enable PWREN signale */
! 244: #define LCDCON5_INVLEND (1<<4) /* TFT: LEND signal polarity */
! 245: #define LCDCON5_INVPWREN (1<<5) /* PWREN signal polarity */
! 246: #define LCDCON5_INVVDEN (1<<6) /* VDEN signal polarity */
! 247: #define LCDCON5_INVVD (1<<7) /* video data signal polarity */
! 248: #define LCDCON5_INVVFRAME (1<<8) /* VFRAME/VSYNC signal polarity */
! 249: #define LCDCON5_INVVLINE (1<<9) /* VLINE/HSYNC signal polarity */
! 250: #define LCDCON5_INVVCLK (1<<10) /* VCLK signal polarity */
! 251: #define LCDCON5_INVVCLK_RISING LCDCON5_INVVCLK
! 252: #define LCDCON5_INVVCLK_FALLING 0
! 253: #define LCDCON5_FRM565 (1<<11) /* RGB:565 format*/
! 254: #define LCDCON5_FRM555I 0 /* RGBI:5551 format */
! 255: #define LCDCON5_BPP24BL (1<<12) /* bit order for bpp24 */
! 256:
! 257: #define LCDCON5_HSTATUS_SHIFT 17 /* TFT: horizontal status */
! 258: #define LCDCON5_HSTATUS_MASK (0x03<<LCDCON5_HSTATUS_SHIFT)
! 259: #define LCDCON5_HSTATUS_HSYNC (0x00<<LCDCON5_HSTATUS_SHIFT)
! 260: #define LCDCON5_HSTATUS_BACKP (0x01<<LCDCON5_HSTATUS_SHIFT)
! 261: #define LCDCON5_HSTATUS_ACTIVE (0x02<<LCDCON5_HSTATUS_SHIFT)
! 262: #define LCDCON5_HSTATUS_FRONTP (0x03<<LCDCON5_HSTATUS_SHIFT)
! 263:
! 264: #define LCDCON5_VSTATUS_SHIFT 19 /* TFT: vertical status */
! 265: #define LCDCON5_VSTATUS_MASK (0x03<<LCDCON5_VSTATUS_SHIFT)
! 266: #define LCDCON5_VSTATUS_HSYNC (0x00<<LCDCON5_VSTATUS_SHIFT)
! 267: #define LCDCON5_VSTATUS_BACKP (0x01<<LCDCON5_VSTATUS_SHIFT)
! 268: #define LCDCON5_VSTATUS_ACTIVE (0x02<<LCDCON5_VSTATUS_SHIFT)
! 269: #define LCDCON5_VSTATUS_FRONTP (0x03<<LCDCON5_VSTATUS_SHIFT)
! 270:
! 271: #define LCDC_LCDSADDR1 0x14 /* frame buffer start address */
! 272: #define LCDC_LCDSADDR2 0x18
! 273: #define LCDC_LCDSADDR3 0x1c
! 274: #define LCDSADDR3_OFFSIZE_SHIFT 11
! 275: #define LCDSADDR3_PAGEWIDTH_SHIFT 0
! 276:
! 277: #define LCDC_REDLUT 0x20 /* STN: red lookup table */
! 278: #define LCDC_GREENLUT 0x24 /* STN: green lookup table */
! 279: #define LCDC_BLUELUT 0x28 /* STN: blue lookup table */
! 280: #define LCDC_DITHMODE 0x4c /* STN: dithering mode */
! 281:
! 282: #define LCDC_TPAL 0x50 /* TFT: temporary palette */
! 283: #define TPAL_TPALEN (1<<24)
! 284: #define TPAL_RED_SHIFT 16
! 285: #define TPAL_GREEN_SHIFT 8
! 286: #define TPAL_BLUE_SHIFT 0
! 287:
! 288: #define LCDC_LCDINTPND 0x54
! 289: #define LCDC_LCDSRCPND 0x58
! 290: #define LCDC_LCDINTMSK 0x5c
! 291: #define LCDINT_FICNT (1<<0) /* FIFO trigger interrupt pending */
! 292: #define LCDINT_FRSYN (1<<1) /* frame sync interrupt pending */
! 293: #define LCDINT_FIWSEL (1<<2) /* FIFO trigger level: 1=8 words, 0=4 words*/
! 294:
! 295: #define LCDC_LPCSEL 0x60 /* LPC3600 mode */
! 296: #define LPCSEL_LPC_EN (1<<0) /* enable LPC3600 mode */
! 297: #define LPCSEL_RES_SEL (1<<1) /* 1=240x320 0=320x240 */
! 298: #define LPCSEL_MODE_SEL (1<<2)
! 299: #define LPCSEL_CPV_SEL (1<<3)
! 300:
! 301:
! 302: #define LCDC_PALETTE 0x0400
! 303: #define LCDC_PALETTE_SIZE 0x0400
! 304:
! 305: #define S3C24X0_LCDC_SIZE (LCDC_PALETTE+LCDC_PALETTE_SIZE)
! 306:
! 307: /* Timer */
! 308: #define TIMER_TCFG0 0x00 /* Timer configuration */
! 309: #define TIMER_TCFG1 0x04
! 310: #define TCFG1_MUX_SHIFT(n) (4*(n))
! 311: #define TCFG1_MUX_MASK(n) (0x0f << TCFG1_MUX_SHIFT(n))
! 312: #define TCFG1_MUX_DIV2 0
! 313: #define TCFG1_MUX_DIV4 1
! 314: #define TCFG1_MUX_DIV8 2
! 315: #define TCFG1_MUX_DIV16 3
! 316: #define TCFG1_MUX_EXT 4
! 317: #define TIMER_TCON 0x08 /* control */
! 318: #define TCON_SHIFT(n) (4 * ((n)==0 ? 0 : (n)+1))
! 319: #define TCON_START(n) (1 << TCON_SHIFT(n))
! 320: #define TCON_MANUALUPDATE(n) (1 << (TCON_SHIFT(n) + 1))
! 321: #define TCON_INVERTER(n) (1 << (TCON_SHIFT(n) + 2))
! 322: #define __TCON_AUTORELOAD(n) (1 << (TCON_SHIFT(n) + 3)) /* n=0..3 */
! 323: #define TCON_AUTORELOAD4 (1<<22) /* stupid hardware design */
! 324: #define TCON_AUTORELOAD(n) ((n)==4 ? TCON_AUTORELOAD4 : __TCON_AUTORELOAD(n))
! 325: #define TCON_MASK(n) (0x0f << TCON_SHIFT(n))
! 326: #define TIMER_TCNTB(n) (0x0c+0x0c*(n)) /* count buffer */
! 327: #define TIMER_TCMPB(n) (0x10+0x0c*(n)) /* compare buffer */
! 328: #define __TIMER_TCNTO(n) (0x14+0x0c*(n)) /* count observation */
! 329: #define TIMER_TCNTO4 0x40
! 330: #define TIMER_TCNTO(n) ((n)==4 ? TIMER_TCNTO4 : __TIMER_TCNTO(n))
! 331:
! 332: #define S3C24X0_TIMER_SIZE 0x44
! 333:
! 334: /* UART */
! 335: /* diffs to s3c2800 */
! 336: #define UMCON_AFC (1<<4) /* auto flow control */
! 337: #define UMSTAT_DCTS (1<<2) /* CTS change */
! 338: #define ULCON_IR (1<<6)
! 339: #define ULCON_PARITY_SHIFT 3
! 340:
! 341: #define S3C24X0_UART_SIZE 0x2c
! 342:
! 343: /* USB device */
! 344: /* XXX */
! 345:
! 346: /* Watch dog timer */
! 347: #define WDT_WTCON 0x00 /* WDT mode */
! 348: #define WTCON_PRESCALE_SHIFT 8
! 349: #define WTCON_PRESCALE (0xff<<WTCON_PRESCALE_SHIFT)
! 350: #define WTCON_ENABLE (1<<5)
! 351: #define WTCON_CLKSEL (3<<3)
! 352: #define WTCON_CLKSEL_16 (0<<3)
! 353: #define WTCON_CLKSEL_32 (1<<3)
! 354: #define WTCON_CLKSEL_64 (2<<3)
! 355: #define WTCON_CLKSEL_128 (3<<3)
! 356: #define WTCON_ENINT (1<<2)
! 357: #define WTCON_ENRST (1<<0)
! 358:
! 359: #define WTCON_WDTSTOP 0
! 360:
! 361: #define WDT_WTDAT 0x04 /* timer data */
! 362: #define WDT_WTCNT 0x08 /* timer count */
! 363:
! 364: #define S3C24X0_WDT_SIZE 0x0c
! 365:
! 366: /* IIC */ /* XXX */
! 367: #define S3C24X0_IIC_SIZE 0x0c
! 368:
! 369:
! 370: /* IIS */ /* XXX */
! 371: #define S3C24X0_IIS_SIZE 0x14
! 372:
! 373: /* RTC */ /* XXX */
! 374:
! 375: /* SPI */
! 376: #define S3C24X0_SPI_SIZE 0x20
! 377:
! 378: #define SPI_SPCON 0x00
! 379: #define SPCON_TAGD (1<<0) /* Tx auto garbage */
! 380: #define SPCON_CPHA (1<<1)
! 381: #define SPCON_CPOL (1<<2)
! 382: #define SPCON_IDLELOW_RISING (0|0)
! 383: #define SPCON_IDLELOW_FALLING (0|SPCON_CPHA)
! 384: #define SPCON_IDLEHIGH_FALLING (SPCON_CPOL|0)
! 385: #define SPCON_IDLEHIGH_RISING (SPCON_CPOL|SPCON_CPHA)
! 386: #define SPCON_MSTR (1<<3)
! 387: #define SPCON_ENSCK (1<<4)
! 388: #define SPCON_SMOD_SHIFT 5
! 389: #define SPCON_SMOD_MASK (0x03<<SPCON_SMOD_SHIFT)
! 390: #define SPCON_SMOD_POLL (0x00<<SPCON_SMOD_SHIFT)
! 391: #define SPCON_SMOD_INT (0x01<<SPCON_SMOD_SHIFT)
! 392: #define SPCON_SMOD_DMA (0x02<<SPCON_SMOD_SHIFT)
! 393:
! 394: #define SPI_SPSTA 0x04 /* status register */
! 395: #define SPSTA_REDY (1<<0) /* ready */
! 396: #define SPSTA_MULF (1<<1) /* multi master error */
! 397: #define SPSTA_DCOL (1<<2) /* Data collision error */
! 398:
! 399: #define SPI_SPPIN 0x08
! 400: #define SPPIN_KEEP (1<<0)
! 401: #define SPPIN_ENMUL (1<<2) /* multi master error detect */
! 402:
! 403: #define SPI_SPPRE 0x0c /* prescaler */
! 404: #define SPI_SPTDAT 0x10 /* tx data */
! 405: #define SPI_SPRDAT 0x14 /* rx data */
! 406:
! 407:
! 408: #endif /* _ARM_S3C2XX0_S3C24X0REG_H_ */
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