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Annotation of sys/arch/arm/s3c2xx0/s3c24x0_intr.h, Revision 1.1

1.1     ! nbrk        1: /*     $NetBSD: s3c24x0_intr.h,v 1.6 2005/12/24 20:06:52 perry Exp $ */
        !             2:
        !             3: /*
        !             4:  * Copyright (c) 2002, 2003  Genetec corporation.  All rights reserved.
        !             5:  * Written by Hiroyuki Bessho for Genetec corporation.
        !             6:  *
        !             7:  * Redistribution and use in source and binary forms, with or without
        !             8:  * modification, are permitted provided that the following conditions
        !             9:  * are met:
        !            10:  * 1. Redistributions of source code must retain the above copyright
        !            11:  *    notice, this list of conditions and the following disclaimer.
        !            12:  * 2. Redistributions in binary form must reproduce the above copyright
        !            13:  *    notice, this list of conditions and the following disclaimer in the
        !            14:  *    documentation and/or other materials provided with the distribution.
        !            15:  * 3. The name of Genetec corporation may not be used to endorse
        !            16:  *    or promote products derived from this software without specific prior
        !            17:  *    written permission.
        !            18:  *
        !            19:  * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
        !            20:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
        !            21:  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
        !            22:  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORP.
        !            23:  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
        !            24:  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
        !            25:  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
        !            26:  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
        !            27:  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
        !            28:  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
        !            29:  * POSSIBILITY OF SUCH DAMAGE.
        !            30:  */
        !            31:
        !            32: #ifndef _S3C24X0_INTR_H_
        !            33: #define        _S3C24X0_INTR_H_
        !            34:
        !            35: #ifndef _LOCORE
        !            36:
        !            37: #define        SI_TO_IRQBIT(si)  (1<<(si))
        !            38:
        !            39: #define        get_pending_softint()   (softint_pending & soft_intr_mask)
        !            40: #define        update_softintr_mask()  \
        !            41:        (soft_intr_mask = s3c24x0_soft_imask[current_spl_level])
        !            42: #define        s3c2xx0_update_hw_mask() \
        !            43:        (*s3c2xx0_intr_mask_reg = ~(intr_mask & global_intr_mask))
        !            44:
        !            45: /* no room for softinterrupts in intr_mask. */
        !            46: extern int volatile soft_intr_mask;
        !            47: extern int s3c24x0_soft_imask[];
        !            48:
        !            49:
        !            50: #include <arm/s3c2xx0/s3c2xx0_intr.h>
        !            51:
        !            52: #endif /* ! _LOCORE */
        !            53:
        !            54: #endif /* _S3C24X0_INTR_H_ */