Annotation of sys/arch/arm/s3c2xx0/s3c2410reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $NetBSD: s3c2410reg.h,v 1.7 2005/12/11 12:16:51 christos Exp $ */
2:
3: /*
4: * Copyright (c) 2003, 2004 Genetec corporation. All rights reserved.
5: * Written by Hiroyuki Bessho for Genetec corporation.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. The name of Genetec corporation may not be used to endorse
16: * or promote products derived from this software without specific prior
17: * written permission.
18: *
19: * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
20: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
23: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29: * POSSIBILITY OF SUCH DAMAGE.
30: */
31:
32:
33: /*
34: * Samsung S3C2410X processor is ARM920T based integrated CPU
35: *
36: * Reference:
37: * S3C2410X User's Manual
38: */
39: #ifndef _ARM_S3C2XX0_S3C2410REG_H_
40: #define _ARM_S3C2XX0_S3C2410REG_H_
41:
42: /* common definitions for S3C2800, S3C2400 and S3C2410 */
43: #include <arm/s3c2xx0/s3c2xx0reg.h>
44: /* common definitions for S3C2400 and S3C2410 */
45: #include <arm/s3c2xx0/s3c24x0reg.h>
46:
47: /*
48: * Memory Map
49: */
50: #define S3C2410_BANK_SIZE 0x08000000
51: #define S3C2410_BANK_START(n) (S3C2410_BANK_SIZE*(n))
52: #define S3C2410_SDRAM_START S3C2410_BANK_START(6)
53:
54: /*
55: * Physical address of integrated peripherals
56: */
57: #define S3C2410_MEMCTL_BASE 0x48000000 /* memory controller */
58: #define S3C2410_USBHC_BASE 0x49000000 /* USB Host controller */
59: #define S3C2410_INTCTL_BASE 0x4a000000 /* Interrupt controller */
60: #define S3C2410_DMAC_BASE 0x4b000000
61: #define S3C2410_DMAC_SIZE 0xe4
62: #define S3C2410_CLKMAN_BASE 0x4c000000 /* clock & power management */
63: #define S3C2410_LCDC_BASE 0x4d000000 /* LCD controller */
64: #define S3C2410_NANDFC_BASE 0x4e000000 /* NAND Flash controller */
65: #define S3C2410_NANDFC_SIZE 0x18
66: #define S3C2410_UART0_BASE 0x50000000
67: #define S3C2410_UART_BASE(n) (S3C2410_UART0_BASE+0x4000*(n))
68: #define S3C2410_TIMER_BASE 0x51000000
69: #define S3C2410_USBDC_BASE 0x5200140
70: #define S3C2410_USBDC_SIZE 0x130
71: #define S3C2410_WDT_BASE 0x53000000
72: #define S3C2410_IIC_BASE 0x54000000
73: #define S3C2410_IIS_BASE 0x55000000
74: #define S3C2410_GPIO_BASE 0x56000000
75: #define S3C2410_GPIO_SIZE 0xb4
76: #define S3C2410_ADC_BASE 0x58000000
77: #define S3C2410_ADC_SIZE 0x14
78: #define S3C2410_SPI0_BASE 0x59000000
79: #define S3C2410_SPI1_BASE 0x59000020
80: #define S3C2410_SDI_BASE 0x5a000000 /* SD Interface */
81: #define S3C2410_SDI_SIZE 0x44
82:
83: /* interrupt control (additional defs for 2410) */
84: #define ICU_LEN (32+11)
85:
86: #define INTCTL_SUBSRCPND 0x18 /* sub source pending (2410 only) */
87: #define INTCTL_INTSUBMSK 0x1c /* sub mask (2410 only) */
88:
89: /* 2410 has more than 32 interrupt sources. These are sub-sources
90: * that are OR-ed into main interrupt sources, and controlled via
91: * SUBSRCPND and SUBSRCMSK registers */
92:
93: #define S3C2410_SUBIRQ_MIN 32
94: #define S3C2410_SUBIRQ_MAX (32+10)
95:
96: /* cascaded to INT_ADCTC */
97: #define S3C2410_INT_ADC (S3C2410_SUBIRQ_MIN+10) /* AD converter */
98: #define S3C2410_INT_TC (S3C2410_SUBIRQ_MIN+9) /* Touch screen */
99: /* cascaded to INT_UART2 */
100: #define S3C2410_INT_ERR2 (S3C2410_SUBIRQ_MIN+8) /* UART2 Error interrupt */
101: #define S3C2410_INT_TXD2 (S3C2410_SUBIRQ_MIN+7) /* UART2 Tx interrupt */
102: #define S3C2410_INT_RXD2 (S3C2410_SUBIRQ_MIN+6) /* UART2 Rx interrupt */
103: /* cascaded to INT_UART1 */
104: #define S3C2410_INT_ERR1 (S3C2410_SUBIRQ_MIN+5) /* UART1 Error interrupt */
105: #define S3C2410_INT_TXD1 (S3C2410_SUBIRQ_MIN+4) /* UART1 Tx interrupt */
106: #define S3C2410_INT_RXD1 (S3C2410_SUBIRQ_MIN+3) /* UART1 Rx interrupt */
107: /* cascaded to INT_UART0 */
108: #define S3C2410_INT_ERR0 (S3C2410_SUBIRQ_MIN+2) /* UART0 Error interrupt */
109: #define S3C2410_INT_TXD0 (S3C2410_SUBIRQ_MIN+1) /* UART0 Tx interrupt */
110: #define S3C2410_INT_RXD0 (S3C2410_SUBIRQ_MIN+0) /* UART0 Rx interrupt */
111:
112: #define S3C2410_INTCTL_SIZE 0x20
113:
114:
115: /* Clock control */
116: #define CLKMAN_LOCKTIME 0x00
117: #define CLKMAN_MPLLCON 0x04
118: #define CLKMAN_UPLLCON 0x08
119: #define CLKMAN_CLKCON 0x0c
120: #define CLKCON_SPI (1<<18)
121: #define CLKCON_IIS (1<<17)
122: #define CLKCON_IIC (1<<16)
123: #define CLKCON_ADC (1<<15)
124: #define CLKCON_RTC (1<<14)
125: #define CLKCON_GPIO (1<<13)
126: #define CLKCON_UART2 (1<<12)
127: #define CLKCON_UART1 (1<<11)
128: #define CLKCON_UART0 (1<<10) /* PCLK to UART0 */
129: #define CLKCON_SDI (1<<9)
130: #define CLKCON_TIMER (1<<8) /* PCLK to TIMER */
131: #define CLKCON_USBD (1<<7) /* PCLK to USB device controller */
132: #define CLKCON_USBH (1<<6) /* PCLK to USB host controller */
133: #define CLKCON_LCDC (1<<5) /* PCLK to LCD controller */
134: #define CLKCON_NANDFC (1<<4) /* PCLK to NAND Flash controller */
135: #define CLKCON_IDLE (1<<2) /* 1=transition to IDLE mode */
136: #define CLKCON_STOP (1<<0) /* 1=transition to STOP mode */
137: #define CLKMAN_CLKSLOW 0x10
138: #define CLKMAN_CLKDIVN 0x14
139: #define CLKDIVN_HDIVN (1<<1) /* hclk=fclk/2 */
140: #define CLKDIVN_PDIVN (1<<0) /* pclk=hclk/2 */
141:
142: /* NAND Flash controller */
143: #define NANDFC_NFCONF 0x00 /* Configuration */
144: #define NANDFC_NFCMD 0x04 /* command */
145: #define NANDFC_NFADDR 0x08 /* address */
146: #define NANDFC_NFDATA 0x0c /* data */
147: #define NANDFC_NFSTAT 0x10 /* operation status */
148: #define NANDFC_NFECC 0x14 /* ecc */
149:
150: /* GPIO */
151: #define GPIO_PACON 0x00 /* port A configuration */
152: #define PCON_INPUT 0 /* Input port */
153: #define PCON_OUTPUT 1 /* Output port */
154: #define PCON_ALTFUN 2 /* Alternate function */
155: #define PCON_ALTFUN2 3 /* Alternate function */
156: #define GPIO_PADAT 0x04 /* port A data */
157: #define GPIO_PBCON 0x10
158: #define GPIO_PBDAT 0x14
159: #define GPIO_PBUP 0x18
160: #define GPIO_PCCON 0x20
161: #define GPIO_PCDAT 0x24
162: #define GPIO_PCUP 0x28
163: #define GPIO_PDCON 0x30
164: #define GPIO_PDDAT 0x34
165: #define GPIO_PDUP 0x38
166: #define GPIO_PECON 0x40
167: #define GPIO_PEDAT 0x44
168: #define GPIO_PEUP 0x48
169: #define GPIO_PFCON 0x50
170: #define GPIO_PFDAT 0x54
171: #define GPIO_PFUP 0x58
172: #define GPIO_PGCON 0x60
173: #define GPIO_PGDAT 0x64
174: #define GPIO_PGUP 0x68
175: #define GPIO_PHCON 0x70
176: #define GPIO_PHDAT 0x74
177: #define GPIO_PHUP 0x78
178: #define GPIO_MISCCR 0x80 /* miscellaneous control */
179: #define GPIO_DCLKCON 0x84 /* DCLK 0/1 */
180: #define GPIO_EXTINT(n) (0x88+4*(n)) /* external int control 0/1/2 */
181: #define GPIO_EINTFLT(n) (0x94+4*(n)) /* external int filter control 0..3 */
182: #define GPIO_EINTMASK 0xa4
183: #define GPIO_EINTPEND 0xa8
184: #define GPIO_GSTATUS0 0xac /* external pin status */
185: #define GPIO_GSTATUS1 0xb0 /* external pin status */
186:
187: #define GPIO_SET_FUNC(v,port,func) \
188: (((v) & ~(3<<(2*(port))))|((func)<<(2*(port))))
189:
190: #define EXTINTR_LOW 0x00
191: #define EXTINTR_HIGH 0x01
192: #define EXTINTR_FALLING 0x02
193: #define EXTINTR_RISING 0x04
194: #define EXTINTR_BOTH 0x06
195:
196: /* SD interface */
197: /* XXX */
198:
199: /* ADC */
200: /* XXX: ADCCON register is common to both S3C2410 and S3C2400,
201: * but other registers are different.
202: */
203: #define ADC_ADCCON 0x00
204: #define ADCCON_ENABLE_START (1<<0)
205: #define ADCCON_READ_START (1<<1)
206: #define ADCCON_STDBM (1<<2)
207: #define ADCCON_SEL_MUX_SHIFT 3
208: #define ADCCON_SEL_MUX_MASK (0x7<<ADCCON_SEL_MUX_SHIFT)
209: #define ADCCON_PRSCVL_SHIFT 6
210: #define ADCCON_PRSCVL_MASK (0xff<<ADCCON_PRSCVL_SHIFT)
211: #define ADCCON_PRSCEN (1<<14)
212: #define ADCCON_ECFLG (1<<15)
213:
214: #define ADC_ADCTSC 0x04
215: #define ADCTSC_XY_PST 0x03
216: #define ADCTSC_AUTO_PST (1<<2)
217: #define ADCTSC_PULL_UP (1<<3)
218: #define ADCTSC_XP_SEN (1<<4)
219: #define ADCTSC_XM_SEN (1<<5)
220: #define ADCTSC_YP_SEN (1<<6)
221: #define ADCTSC_YM_SEN (1<<7)
222: #define ADCTSC_UD_SEN (1<<8)
223: #define ADC_ADCDLY 0x08
224: #define ADC_ADCDAT0 0x0c
225: #define ADC_ADCDAT1 0x10
226:
227: #define ADCDAT_DATAMASK 0x3ff
228:
229: #endif /* _ARM_S3C2XX0_S3C2410REG_H_ */
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