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Annotation of sys/arch/arm/s3c2xx0/s3c2400reg.h, Revision 1.1

1.1     ! nbrk        1: /* $NetBSD: s3c2400reg.h,v 1.4 2005/12/11 12:16:51 christos Exp $ */
        !             2:
        !             3: /*
        !             4:  * Copyright (c) 2002, 2003  Genetec corp.  All rights reserved.
        !             5:  * Written by Hiroyuki Bessho for Genetec corp.
        !             6:  *
        !             7:  * Redistribution and use in source and binary forms, with or without
        !             8:  * modification, are permitted provided that the following conditions
        !             9:  * are met:
        !            10:  * 1. Redistributions of source code must retain the above copyright
        !            11:  *    notice, this list of conditions and the following disclaimer.
        !            12:  * 2. Redistributions in binary form must reproduce the above copyright
        !            13:  *    notice, this list of conditions and the following disclaimer in the
        !            14:  *    documentation and/or other materials provided with the distribution.
        !            15:  * 3. The name of Genetec corporation may not be used to endorse
        !            16:  *    or promote products derived from this software without specific prior
        !            17:  *    written permission.
        !            18:  *
        !            19:  * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
        !            20:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
        !            21:  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
        !            22:  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORP.
        !            23:  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
        !            24:  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
        !            25:  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
        !            26:  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
        !            27:  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
        !            28:  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
        !            29:  * POSSIBILITY OF SUCH DAMAGE.
        !            30:  */
        !            31:
        !            32:
        !            33: /*
        !            34:  * Samsung S3C2400 processor is ARM920T based integrated CPU
        !            35:  *
        !            36:  * Reference:
        !            37:  *  S3C2400X User's Manual
        !            38:  */
        !            39: #ifndef _ARM_S3C2400_S3C24X0REG_H_
        !            40: #define        _ARM_S3C2400_S3C24X0REG_H_
        !            41:
        !            42: /* common definitions for S3C2800, S3C2400X and S3C2410X */
        !            43: #include <arm/s3c2xx0/s3c2xx0reg.h>
        !            44:
        !            45: /*
        !            46:  * Memory Map
        !            47:  */
        !            48:
        !            49: #define        S3C2400_BANK_START(n)   (0x02000000*(n))
        !            50: #define        S3C2400_SDRAM_START     S3C2400_BANK_START(6)
        !            51: #define        S3C2400_AHB_START       0x14000000
        !            52: #define        S3C2400_APB_START       0x15000000
        !            53:
        !            54: /*
        !            55:  * Physical address of integrated peripherals
        !            56:  */
        !            57: #define        S3C2400_MEMCTL_BASE     0x14000000 /* memory controller */
        !            58: #define        S3C2400_USBHC_BASE      0x14200000 /* USB Host controller */
        !            59: #define        S3C2400_INTCTL_BASE     0x14400000 /* Interrupt controller */
        !            60: #define        S3C2400_INTCTL_SIZE     0x18
        !            61: #define        S3C2400_DMAC_BASE       0x14600000 /* DMA controllers */
        !            62: #define        S3C2400_DMAC_SIZE       0x80
        !            63: #define        S3C2400_CLKMAN_BASE     0x14800000 /* clock & power management */
        !            64: #define        S3C2400_CLKMAN_SIZE     0x18
        !            65: #define        S3C2400_LCDC_BASE       0x14a00000
        !            66: #define        S3C2400_UART_BASE       0x15000000
        !            67: #define        S3C2400_UART_BASE(n)    (S3C2400_UART_BASE+0x4000*(n))
        !            68: #define        S3C2400_TIMER_BASE      0x15100000 /* Timers */
        !            69: #define        S3C2400_USBDC_BASE      0x15200000 /* USB Device controller */
        !            70: #define        S3C2400_USBDC_SIZE      0x1fc
        !            71: #define        S3C2400_WDT_BASE        0x15300000 /* Watch dog timer */
        !            72: #define        S3C2400_IIC_BASE        0x15400000
        !            73: #define        S3C2400_IIS_BASE        0x15508000
        !            74: #define        S3C2400_GPIO_BASE       0x15600000
        !            75: #define        S3C2400_GPIO_SIZE       0x5c
        !            76: #define        S3C2400_RTC_BASE        0x15700040
        !            77: #define        S3C2400_RTC_SIZE        0x4c
        !            78: #define        S3C2400_ADC_BASE        0x15800000 /* A/D converter */
        !            79: #define        S3C2400_ADC_SIZE        0x08
        !            80: #define        S3C2400_SPI_BASE        0x15900000
        !            81: #define        S3C2400_MMC_BASE        0x15a00000
        !            82: #define        S3C2400_MMC_SIZE        0x40
        !            83:
        !            84: /* GPIO */
        !            85: #define        GPIO_PACON      0x00    /* port A configuration */
        !            86: #define         PCON_INPUT     0       /* Input port */
        !            87: #define         PCON_OUTPUT    1       /* Output port */
        !            88: #define         PCON_ALTFUN    2       /* Alternate function */
        !            89: #define        GPIO_PADAT      0x04    /* port A data */
        !            90: #define        GPIO_PBCON      0x08
        !            91: #define        GPIO_PBDAT      0x0c
        !            92: #define        GPIO_PBUP       0x10
        !            93: #define        GPIO_PCCON      0x14
        !            94: #define        GPIO_PCDAT      0x18
        !            95: #define        GPIO_PCUP       0x1c
        !            96: #define        GPIO_PDCON      0x20
        !            97: #define        GPIO_PDDAT      0x24
        !            98: #define        GPIO_PDUP       0x28
        !            99: #define        GPIO_PECON      0x3c
        !           100: #define        GPIO_PEDAT      0x30
        !           101: #define        GPIO_PEUP       0x34
        !           102: #define        GPIO_PFCON      0x38
        !           103: #define        GPIO_PFDAT      0x3c
        !           104: #define        GPIO_PFUP       0x40
        !           105: #define        GPIO_PGCON      0x44
        !           106: #define        GPIO_PGDAT      0x49
        !           107: #define        GPIO_PGUP       0x4c
        !           108: #define        GPIO_OPENCR     0x50    /* Open drain enable */
        !           109: #define        GPIO_MISCCR     0x54    /* miscellaneous control */
        !           110:
        !           111: #define        GPIO_EXTINTR    0x48    /* external interrupt control */
        !           112: #define         EXTINTR_LOW     0x00
        !           113: #define         EXTINTR_HIGH    0x01
        !           114: #define         EXTINTR_FALLING 0x02
        !           115: #define         EXTINTR_RISING  0x04
        !           116: #define         EXTINTR_BOTH    0x06
        !           117:
        !           118: /* MMC */ /* XXX */
        !           119:
        !           120: #endif /* _ARM_S3C2400_S3C2400REG_H_ */