Annotation of sys/arch/arm/include/pte.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: pte.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */
2: /* $NetBSD: pte.h,v 1.6 2003/04/18 11:08:28 scw Exp $ */
3:
4: /*
5: * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
6: * All rights reserved.
7: *
8: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed for the NetBSD Project by
21: * Wasabi Systems, Inc.
22: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23: * or promote products derived from this software without specific prior
24: * written permission.
25: *
26: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36: * POSSIBILITY OF SUCH DAMAGE.
37: */
38:
39: #ifndef _ARM_PTE_H_
40: #define _ARM_PTE_H_
41:
42: /*
43: * The ARM MMU architecture was introduced with ARM v3 (previous ARM
44: * architecture versions used an optional off-CPU memory controller
45: * to perform address translation).
46: *
47: * The ARM MMU consists of a TLB and translation table walking logic.
48: * There is typically one TLB per memory interface (or, put another
49: * way, one TLB per software-visible cache).
50: *
51: * The ARM MMU is capable of mapping memory in the following chunks:
52: *
53: * 1M Sections (L1 table)
54: *
55: * 64K Large Pages (L2 table)
56: *
57: * 4K Small Pages (L2 table)
58: *
59: * 1K Tiny Pages (L2 table)
60: *
61: * There are two types of L2 tables: Coarse Tables and Fine Tables.
62: * Coarse Tables can map Large and Small Pages. Fine Tables can
63: * map Tiny Pages.
64: *
65: * Coarse Tables can define 4 Subpages within Large and Small pages.
66: * Subpages define different permissions for each Subpage within
67: * a Page.
68: *
69: * Coarse Tables are 1K in length. Fine tables are 4K in length.
70: *
71: * The Translation Table Base register holds the pointer to the
72: * L1 Table. The L1 Table is a 16K contiguous chunk of memory
73: * aligned to a 16K boundary. Each entry in the L1 Table maps
74: * 1M of virtual address space, either via a Section mapping or
75: * via an L2 Table.
76: *
77: * In addition, the Fast Context Switching Extension (FCSE) is available
78: * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating
79: * TLB/cache flushes on context switch by use of a smaller address space
80: * and a "process ID" that modifies the virtual address before being
81: * presented to the translation logic.
82: */
83:
84: #ifndef _LOCORE
85: typedef uint32_t pd_entry_t; /* L1 table entry */
86: typedef uint32_t pt_entry_t; /* L2 table entry */
87: #endif /* _LOCORE */
88:
89: #define L1_S_SIZE 0x00100000 /* 1M */
90: #define L1_S_OFFSET (L1_S_SIZE - 1)
91: #define L1_S_FRAME (~L1_S_OFFSET)
92: #define L1_S_SHIFT 20
93:
94: #define L2_L_SIZE 0x00010000 /* 64K */
95: #define L2_L_OFFSET (L2_L_SIZE - 1)
96: #define L2_L_FRAME (~L2_L_OFFSET)
97: #define L2_L_SHIFT 16
98:
99: #define L2_S_SIZE 0x00001000 /* 4K */
100: #define L2_S_OFFSET (L2_S_SIZE - 1)
101: #define L2_S_FRAME (~L2_S_OFFSET)
102: #define L2_S_SHIFT 12
103:
104: #define L2_T_SIZE 0x00000400 /* 1K */
105: #define L2_T_OFFSET (L2_T_SIZE - 1)
106: #define L2_T_FRAME (~L2_T_OFFSET)
107: #define L2_T_SHIFT 10
108:
109: /*
110: * The NetBSD VM implementation only works on whole pages (4K),
111: * whereas the ARM MMU's Coarse tables are sized in terms of 1K
112: * (16K L1 table, 1K L2 table).
113: *
114: * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2
115: * table.
116: */
117: #define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */
118: #define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */
119:
120: #define L1_TABLE_SIZE 0x4000 /* 16K */
121: #define L2_TABLE_SIZE 0x1000 /* 4K */
122: /*
123: * The new pmap deals with the 1KB coarse L2 tables by
124: * allocating them from a pool. Until every port has been converted,
125: * keep the old L2_TABLE_SIZE define lying around. Converted ports
126: * should use L2_TABLE_SIZE_REAL until then.
127: */
128: #define L2_TABLE_SIZE_REAL 0x400 /* 1K */
129:
130: /*
131: * ARM L1 Descriptors
132: */
133:
134: #define L1_TYPE_INV 0x00 /* Invalid (fault) */
135: #define L1_TYPE_C 0x01 /* Coarse L2 */
136: #define L1_TYPE_S 0x02 /* Section */
137: #define L1_TYPE_F 0x03 /* Fine L2 */
138: #define L1_TYPE_MASK 0x03 /* mask of type bits */
139:
140: /* L1 Section Descriptor */
141: #define L1_S_B 0x00000004 /* bufferable Section */
142: #define L1_S_C 0x00000008 /* cacheable Section */
143: #define L1_S_IMP 0x00000010 /* implementation defined */
144: #define L1_S_DOM(x) ((x) << 5) /* domain */
145: #define L1_S_DOM_MASK L1_S_DOM(0xf)
146: #define L1_S_AP(x) ((x) << 10) /* access permissions */
147: #define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */
148:
149: #define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */
150: #define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */
151:
152: /* L1 Coarse Descriptor */
153: #define L1_C_IMP0 0x00000004 /* implementation defined */
154: #define L1_C_IMP1 0x00000008 /* implementation defined */
155: #define L1_C_IMP2 0x00000010 /* implementation defined */
156: #define L1_C_DOM(x) ((x) << 5) /* domain */
157: #define L1_C_DOM_MASK L1_C_DOM(0xf)
158: #define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */
159:
160: #define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */
161:
162: /* L1 Fine Descriptor */
163: #define L1_F_IMP0 0x00000004 /* implementation defined */
164: #define L1_F_IMP1 0x00000008 /* implementation defined */
165: #define L1_F_IMP2 0x00000010 /* implementation defined */
166: #define L1_F_DOM(x) ((x) << 5) /* domain */
167: #define L1_F_DOM_MASK L1_F_DOM(0xf)
168: #define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */
169:
170: #define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */
171:
172: /*
173: * ARM L2 Descriptors
174: */
175:
176: #define L2_TYPE_INV 0x00 /* Invalid (fault) */
177: #define L2_TYPE_L 0x01 /* Large Page */
178: #define L2_TYPE_S 0x02 /* Small Page */
179: #define L2_TYPE_T 0x03 /* Tiny Page */
180: #define L2_TYPE_MASK 0x03 /* mask of type bits */
181:
182: /*
183: * This L2 Descriptor type is available on XScale processors
184: * when using a Coarse L1 Descriptor. The Extended Small
185: * Descriptor has the same format as the XScale Tiny Descriptor,
186: * but describes a 4K page, rather than a 1K page.
187: */
188: #define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */
189:
190: #define L2_B 0x00000004 /* Bufferable page */
191: #define L2_C 0x00000008 /* Cacheable page */
192: #define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */
193: #define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */
194: #define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */
195: #define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */
196: #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
197:
198: #define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */
199: #define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */
200:
201: /*
202: * Access Permissions for L1 and L2 Descriptors.
203: */
204: #define AP_W 0x01 /* writable */
205: #define AP_U 0x02 /* user */
206:
207: /*
208: * Short-hand for common AP_* constants.
209: *
210: * Note: These values assume the S (System) bit is set and
211: * the R (ROM) bit is clear in CP15 register 1.
212: */
213: #define AP_KR 0x00 /* kernel read */
214: #define AP_KRW 0x01 /* kernel read/write */
215: #define AP_KRWUR 0x02 /* kernel read/write usr read */
216: #define AP_KRWURW 0x03 /* kernel read/write usr read/write */
217:
218: /*
219: * Domain Types for the Domain Access Control Register.
220: */
221: #define DOMAIN_FAULT 0x00 /* no access */
222: #define DOMAIN_CLIENT 0x01 /* client */
223: #define DOMAIN_RESERVED 0x02 /* reserved */
224: #define DOMAIN_MANAGER 0x03 /* manager */
225:
226: /*
227: * Type Extension bits for XScale processors.
228: *
229: * Behavior of C and B when X == 0:
230: *
231: * C B Cacheable Bufferable Write Policy Line Allocate Policy
232: * 0 0 N N - -
233: * 0 1 N Y - -
234: * 1 0 Y Y Write-through Read Allocate
235: * 1 1 Y Y Write-back Read Allocate
236: *
237: * Behavior of C and B when X == 1:
238: * C B Cacheable Bufferable Write Policy Line Allocate Policy
239: * 0 0 - - - - DO NOT USE
240: * 0 1 N Y - -
241: * 1 0 Mini-Data - - -
242: * 1 1 Y Y Write-back R/W Allocate
243: */
244: #define TEX_XSCALE_X 0x01 /* X modifies C and B */
245:
246: #endif /* _ARM_PTE_H_ */
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