Annotation of sys/arch/arm/include/cpuconf.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cpuconf.h,v 1.3 2006/05/27 20:36:05 miod Exp $ */
2: /* $NetBSD: cpuconf.h,v 1.7 2003/05/23 00:57:24 ichiro Exp $ */
3:
4: /*
5: * Copyright (c) 2002 Wasabi Systems, Inc.
6: * All rights reserved.
7: *
8: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed for the NetBSD Project by
21: * Wasabi Systems, Inc.
22: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23: * or promote products derived from this software without specific prior
24: * written permission.
25: *
26: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36: * POSSIBILITY OF SUCH DAMAGE.
37: */
38:
39: #ifndef _ARM_CPUCONF_H_
40: #define _ARM_CPUCONF_H_
41:
42: /*
43: * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
44: * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm/pmap.h> FOR THE CPU TYPE
45: * YOU ARE ADDING SUPPORT FOR.
46: */
47:
48: /*
49: * Determine which ARM architecture versions are configured.
50: */
51: #if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
52: #define ARM_ARCH_2 1
53: #else
54: #define ARM_ARCH_2 0
55: #endif
56:
57: #if (defined(CPU_ARM6) || defined(CPU_ARM7))
58: #define ARM_ARCH_3 1
59: #else
60: #define ARM_ARCH_3 0
61: #endif
62:
63: #if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
64: defined(CPU_ARM10) || defined(CPU_SA1) || defined(CPU_SA110) || \
65: defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425))
66: #define ARM_ARCH_4 1
67: #else
68: #define ARM_ARCH_4 0
69: #endif
70:
71: #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
72: defined(CPU_XSCALE_PXA2X0))
73: #define ARM_ARCH_5 1
74: #else
75: #define ARM_ARCH_5 0
76: #endif
77:
78: /*
79: * Define which MMU classes are configured:
80: *
81: * ARM_MMU_MEMC Prehistoric, external memory controller
82: * and MMU for ARMv2 CPUs.
83: *
84: * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6.
85: *
86: * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic
87: * ARM MMU, but has no write-through cache mode.
88: *
89: * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM
90: * MMU, but also has several extensions which
91: * require different PTE layout to use.
92: */
93: #if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
94: #define ARM_MMU_MEMC 1
95: #else
96: #define ARM_MMU_MEMC 0
97: #endif
98:
99: #if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
100: defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM10))
101: #define ARM_MMU_GENERIC 1
102: #else
103: #define ARM_MMU_GENERIC 0
104: #endif
105:
106: #if (defined(CPU_SA1) || defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
107: defined(CPU_IXP12X0))
108: #define ARM_MMU_SA1 1
109: #else
110: #define ARM_MMU_SA1 0
111: #endif
112:
113: #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
114: defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
115: #define ARM_MMU_XSCALE 1
116: #else
117: #define ARM_MMU_XSCALE 0
118: #endif
119:
120: #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \
121: ARM_MMU_SA1 + ARM_MMU_XSCALE)
122:
123: /*
124: * Define features that may be present on a subset of CPUs
125: *
126: * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321
127: */
128:
129: #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321))
130: #define ARM_XSCALE_PMU 1
131: #else
132: #define ARM_XSCALE_PMU 0
133: #endif
134:
135: #endif /* _ARM_CPUCONF_H_ */
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