Annotation of sys/arch/arm/include/armreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: armreg.h,v 1.3 2006/05/29 17:01:42 drahn Exp $ */
! 2: /* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1998, 2001 Ben Harris
! 6: * Copyright (c) 1994-1996 Mark Brinicombe.
! 7: * Copyright (c) 1994 Brini.
! 8: * All rights reserved.
! 9: *
! 10: * This code is derived from software written for Brini by Mark Brinicombe
! 11: *
! 12: * Redistribution and use in source and binary forms, with or without
! 13: * modification, are permitted provided that the following conditions
! 14: * are met:
! 15: * 1. Redistributions of source code must retain the above copyright
! 16: * notice, this list of conditions and the following disclaimer.
! 17: * 2. Redistributions in binary form must reproduce the above copyright
! 18: * notice, this list of conditions and the following disclaimer in the
! 19: * documentation and/or other materials provided with the distribution.
! 20: * 3. All advertising materials mentioning features or use of this software
! 21: * must display the following acknowledgement:
! 22: * This product includes software developed by Brini.
! 23: * 4. The name of the company nor the name of the author may be used to
! 24: * endorse or promote products derived from this software without specific
! 25: * prior written permission.
! 26: *
! 27: * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
! 28: * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
! 29: * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 30: * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
! 31: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 32: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 33: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 34: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 35: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 36: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 37: * SUCH DAMAGE.
! 38: */
! 39:
! 40: #ifndef _ARM_ARMREG_H
! 41: #define _ARM_ARMREG_H
! 42:
! 43: /*
! 44: * ARM Process Status Register
! 45: *
! 46: * The picture in the ARM manuals looks like this:
! 47: * 3 3 2 2 2 2
! 48: * 1 0 9 8 7 6 8 7 6 5 4 0
! 49: * +-+-+-+-+-+-------------------------------------+-+-+-+---------+
! 50: * |N|Z|C|V|Q| reserved |I|F|T|M M M M M|
! 51: * | | | | | | | | | |4 3 2 1 0|
! 52: * +-+-+-+-+-+-------------------------------------+-+-+-+---------+
! 53: */
! 54:
! 55: #define PSR_FLAGS 0xf0000000 /* flags */
! 56: #define PSR_N_bit (1 << 31) /* negative */
! 57: #define PSR_Z_bit (1 << 30) /* zero */
! 58: #define PSR_C_bit (1 << 29) /* carry */
! 59: #define PSR_V_bit (1 << 28) /* overflow */
! 60:
! 61: #define PSR_Q_bit (1 << 27) /* saturation */
! 62:
! 63: #define I32_bit (1 << 7) /* IRQ disable */
! 64: #define F32_bit (1 << 6) /* FIQ disable */
! 65:
! 66: #define PSR_T_bit (1 << 5) /* Thumb state */
! 67: #define PSR_J_bit (1 << 24) /* Java mode */
! 68:
! 69: #define PSR_MODE 0x0000001f /* mode mask */
! 70: #define PSR_USR26_MODE 0x00000000
! 71: #define PSR_FIQ26_MODE 0x00000001
! 72: #define PSR_IRQ26_MODE 0x00000002
! 73: #define PSR_SVC26_MODE 0x00000003
! 74: #define PSR_USR32_MODE 0x00000010
! 75: #define PSR_FIQ32_MODE 0x00000011
! 76: #define PSR_IRQ32_MODE 0x00000012
! 77: #define PSR_SVC32_MODE 0x00000013
! 78: #define PSR_ABT32_MODE 0x00000017
! 79: #define PSR_UND32_MODE 0x0000001b
! 80: #define PSR_SYS32_MODE 0x0000001f
! 81: #define PSR_32_MODE 0x00000010
! 82:
! 83: #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */
! 84: #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE)
! 85:
! 86: /* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */
! 87:
! 88: #define R15_MODE 0x00000003
! 89: #define R15_MODE_USR 0x00000000
! 90: #define R15_MODE_FIQ 0x00000001
! 91: #define R15_MODE_IRQ 0x00000002
! 92: #define R15_MODE_SVC 0x00000003
! 93:
! 94: #define R15_PC 0x03fffffc
! 95:
! 96: #define R15_FIQ_DISABLE 0x04000000
! 97: #define R15_IRQ_DISABLE 0x08000000
! 98:
! 99: #define R15_FLAGS 0xf0000000
! 100: #define R15_FLAG_N 0x80000000
! 101: #define R15_FLAG_Z 0x40000000
! 102: #define R15_FLAG_C 0x20000000
! 103: #define R15_FLAG_V 0x10000000
! 104:
! 105: /*
! 106: * Co-processor 15: The system control co-processor.
! 107: */
! 108:
! 109: #define ARM_CP15_CPU_ID 0
! 110:
! 111: /*
! 112: * The CPU ID register is theoretically structured, but the definitions of
! 113: * the fields keep changing.
! 114: */
! 115:
! 116: /* The high-order byte is always the implementor */
! 117: #define CPU_ID_IMPLEMENTOR_MASK 0xff000000
! 118: #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
! 119: #define CPU_ID_DEC 0x44000000 /* 'D' */
! 120: #define CPU_ID_INTEL 0x69000000 /* 'i' */
! 121: #define CPU_ID_TI 0x54000000 /* 'T' */
! 122:
! 123: /* How to decide what format the CPUID is in. */
! 124: #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000)
! 125: #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000)
! 126: #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
! 127:
! 128: /* On ARM3 and ARM6, this byte holds the foundry ID. */
! 129: #define CPU_ID_FOUNDRY_MASK 0x00ff0000
! 130: #define CPU_ID_FOUNDRY_VLSI 0x00560000
! 131:
! 132: /* On ARM7 it holds the architecture and variant (sub-model) */
! 133: #define CPU_ID_7ARCH_MASK 0x00800000
! 134: #define CPU_ID_7ARCH_V3 0x00000000
! 135: #define CPU_ID_7ARCH_V4T 0x00800000
! 136: #define CPU_ID_7VARIANT_MASK 0x007f0000
! 137:
! 138: /* On more recent ARMs, it does the same, but in a different format */
! 139: #define CPU_ID_ARCH_MASK 0x000f0000
! 140: #define CPU_ID_ARCH_V3 0x00000000
! 141: #define CPU_ID_ARCH_V4 0x00010000
! 142: #define CPU_ID_ARCH_V4T 0x00020000
! 143: #define CPU_ID_ARCH_V5 0x00030000
! 144: #define CPU_ID_ARCH_V5T 0x00040000
! 145: #define CPU_ID_ARCH_V5TE 0x00050000
! 146: #define CPU_ID_VARIANT_MASK 0x00f00000
! 147:
! 148: /* Next three nybbles are part number */
! 149: #define CPU_ID_PARTNO_MASK 0x0000fff0
! 150:
! 151: /* Intel XScale has sub fields in part number */
! 152: #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */
! 153: #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */
! 154: #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */
! 155:
! 156: /* And finally, the revision number. */
! 157: #define CPU_ID_REVISION_MASK 0x0000000f
! 158:
! 159: /* Individual CPUs are probably best IDed by everything but the revision. */
! 160: #define CPU_ID_CPU_MASK 0xfffffff0
! 161:
! 162: /* Fake CPU IDs for ARMs without CP15 */
! 163: #define CPU_ID_ARM2 0x41560200
! 164: #define CPU_ID_ARM250 0x41560250
! 165:
! 166: /* Pre-ARM7 CPUs -- [15:12] == 0 */
! 167: #define CPU_ID_ARM3 0x41560300
! 168: #define CPU_ID_ARM600 0x41560600
! 169: #define CPU_ID_ARM610 0x41560610
! 170: #define CPU_ID_ARM620 0x41560620
! 171:
! 172: /* ARM7 CPUs -- [15:12] == 7 */
! 173: #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */
! 174: #define CPU_ID_ARM710 0x41007100
! 175: #define CPU_ID_ARM7500 0x41027100 /* XXX This is a guess. */
! 176: #define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */
! 177: #define CPU_ID_ARM7500FE 0x41077100
! 178: #define CPU_ID_ARM710T 0x41807100
! 179: #define CPU_ID_ARM720T 0x41807200
! 180: #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */
! 181: #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */
! 182:
! 183: /* Post-ARM7 CPUs */
! 184: #define CPU_ID_ARM810 0x41018100
! 185: #define CPU_ID_ARM920T 0x41129200
! 186: #define CPU_ID_ARM922T 0x41029220
! 187: #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */
! 188: #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
! 189: #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
! 190: #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
! 191: #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */
! 192: #define CPU_ID_ARM1022ES 0x4105a220
! 193: #define CPU_ID_SA110 0x4401a100
! 194: #define CPU_ID_SA1100 0x4401a110
! 195: #define CPU_ID_TI925T 0x54029250
! 196: #define CPU_ID_SA1110 0x6901b110
! 197: #define CPU_ID_IXP1200 0x6901c120
! 198: #define CPU_ID_80200 0x69052000
! 199: #define CPU_ID_PXA250 0x69052100 /* sans core revision */
! 200: #define CPU_ID_PXA210 0x69052120
! 201: #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */
! 202: #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */
! 203: #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */
! 204: #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */
! 205: #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */
! 206: #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */
! 207: #define CPU_ID_80219_400 0x69052e20
! 208: #define CPU_ID_80219_600 0x69052e30
! 209: #define CPU_ID_PXA27X 0x69054110
! 210: #define CPU_ID_80321_400 0x69052420
! 211: #define CPU_ID_80321_600 0x69052430
! 212: #define CPU_ID_80321_400_B0 0x69052c20
! 213: #define CPU_ID_80321_600_B0 0x69052c30
! 214: #define CPU_ID_IXP425_533 0x690541c0
! 215: #define CPU_ID_IXP425_400 0x690541d0
! 216: #define CPU_ID_IXP425_266 0x690541f0
! 217:
! 218: /* ARM3-specific coprocessor 15 registers */
! 219: #define ARM3_CP15_FLUSH 1
! 220: #define ARM3_CP15_CONTROL 2
! 221: #define ARM3_CP15_CACHEABLE 3
! 222: #define ARM3_CP15_UPDATEABLE 4
! 223: #define ARM3_CP15_DISRUPTIVE 5
! 224:
! 225: /* ARM3 Control register bits */
! 226: #define ARM3_CTL_CACHE_ON 0x00000001
! 227: #define ARM3_CTL_SHARED 0x00000002
! 228: #define ARM3_CTL_MONITOR 0x00000004
! 229:
! 230: /*
! 231: * Post-ARM3 CP15 registers:
! 232: *
! 233: * 1 Control register
! 234: *
! 235: * 2 Translation Table Base
! 236: *
! 237: * 3 Domain Access Control
! 238: *
! 239: * 4 Reserved
! 240: *
! 241: * 5 Fault Status
! 242: *
! 243: * 6 Fault Address
! 244: *
! 245: * 7 Cache/write-buffer Control
! 246: *
! 247: * 8 TLB Control
! 248: *
! 249: * 9 Cache Lockdown
! 250: *
! 251: * 10 TLB Lockdown
! 252: *
! 253: * 11 Reserved
! 254: *
! 255: * 12 Reserved
! 256: *
! 257: * 13 Process ID (for FCSE)
! 258: *
! 259: * 14 Reserved
! 260: *
! 261: * 15 Implementation Dependent
! 262: */
! 263:
! 264: /* Some of the definitions below need cleaning up for V3/V4 architectures */
! 265:
! 266: /* CPU control register (CP15 register 1) */
! 267: #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */
! 268: #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
! 269: #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
! 270: #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
! 271: #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
! 272: #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
! 273: #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
! 274: #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
! 275: #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
! 276: #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
! 277: #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
! 278: #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
! 279: #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
! 280: #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
! 281: #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
! 282: #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
! 283:
! 284: #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
! 285:
! 286: /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
! 287: #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
! 288: #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
! 289: #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
! 290: #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
! 291: #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
! 292: #define XSCALE_AUXCTL_MD_MASK 0x00000030
! 293:
! 294: /* Cache type register definitions */
! 295: #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
! 296: #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
! 297: #define CPU_CT_S (1U << 24) /* split cache */
! 298: #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
! 299:
! 300: #define CPU_CT_CTYPE_WT 0 /* write-through */
! 301: #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
! 302: #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
! 303: #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
! 304: #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
! 305:
! 306: #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
! 307: #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */
! 308: #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
! 309: #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
! 310:
! 311: /* Fault status register definitions */
! 312:
! 313: #define FAULT_TYPE_MASK 0x0f
! 314: #define FAULT_USER 0x10
! 315:
! 316: #define FAULT_WRTBUF_0 0x00 /* Vector Exception */
! 317: #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */
! 318: #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */
! 319: #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */
! 320: #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */
! 321: #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */
! 322: #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */
! 323: #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */
! 324: #define FAULT_ALIGN_0 0x01 /* Alignment */
! 325: #define FAULT_ALIGN_1 0x03 /* Alignment */
! 326: #define FAULT_TRANS_S 0x05 /* Translation -- Section */
! 327: #define FAULT_TRANS_P 0x07 /* Translation -- Page */
! 328: #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */
! 329: #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */
! 330: #define FAULT_PERM_S 0x0d /* Permission -- Section */
! 331: #define FAULT_PERM_P 0x0f /* Permission -- Page */
! 332:
! 333: #define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */
! 334:
! 335: /*
! 336: * Address of the vector page, low and high versions.
! 337: */
! 338: #define ARM_VECTORS_LOW 0x00000000U
! 339: #define ARM_VECTORS_HIGH 0xffff0000U
! 340:
! 341: /*
! 342: * ARM Instructions
! 343: *
! 344: * 3 3 2 2 2
! 345: * 1 0 9 8 7 0
! 346: * +-------+-------------------------------------------------------+
! 347: * | cond | instruction dependant |
! 348: * |c c c c| |
! 349: * +-------+-------------------------------------------------------+
! 350: */
! 351:
! 352: #define INSN_SIZE 4 /* Always 4 bytes */
! 353: #define INSN_COND_MASK 0xf0000000 /* Condition mask */
! 354: #define INSN_COND_AL 0xe0000000 /* Always condition */
! 355:
! 356: #endif
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