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Annotation of sys/arch/arm/arm/vectors.S, Revision 1.1.1.1

1.1       nbrk        1: /*     $OpenBSD: vectors.S,v 1.1 2004/02/01 05:09:48 drahn Exp $       */
                      2: /*     $NetBSD: vectors.S,v 1.4 2002/08/17 16:36:32 thorpej Exp $      */
                      3:
                      4: /*
                      5:  * Copyright (C) 1994-1997 Mark Brinicombe
                      6:  * Copyright (C) 1994 Brini
                      7:  * All rights reserved.
                      8:  *
                      9:  * Redistribution and use in source and binary forms, with or without
                     10:  * modification, are permitted provided that the following conditions
                     11:  * are met:
                     12:  * 1. Redistributions of source code must retain the above copyright
                     13:  *    notice, this list of conditions and the following disclaimer.
                     14:  * 2. Redistributions in binary form must reproduce the above copyright
                     15:  *    notice, this list of conditions and the following disclaimer in the
                     16:  *    documentation and/or other materials provided with the distribution.
                     17:  * 3. All advertising materials mentioning features or use of this software
                     18:  *    must display the following acknowledgement:
                     19:  *     This product includes software developed by Brini.
                     20:  * 4. The name of Brini may not be used to endorse or promote products
                     21:  *    derived from this software without specific prior written permission.
                     22:  *
                     23:  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
                     24:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
                     25:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
                     26:  * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
                     27:  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
                     28:  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
                     29:  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
                     30:  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
                     31:  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
                     32:  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
                     33:  */
                     34:
                     35: #include "assym.h"
                     36: #include <machine/asm.h>
                     37:
                     38: /*
                     39:  * These are the exception vectors copied down to page 0.
                     40:  *
                     41:  * Note that FIQs are special; rather than using a level of
                     42:  * indirection, we actually copy the FIQ code down into the
                     43:  * vector page.
                     44:  */
                     45:
                     46:        .text
                     47:        .align  0
                     48:        .global _C_LABEL(page0), _C_LABEL(page0_data), _C_LABEL(page0_end)
                     49:        .global _C_LABEL(fiqvector)
                     50:
                     51: _C_LABEL(page0):
                     52:        ldr     pc, .Lreset_target
                     53:        ldr     pc, .Lundefined_target
                     54:        ldr     pc, .Lswi_target
                     55:        ldr     pc, .Lprefetch_abort_target
                     56:        ldr     pc, .Ldata_abort_target
                     57:        ldr     pc, .Laddress_exception_target
                     58:        ldr     pc, .Lirq_target
                     59: #ifdef __ARM_FIQ_INDIRECT
                     60:        ldr     pc, .Lfiq_target
                     61: #else
                     62: .Lfiqvector:
                     63:        .set    _C_LABEL(fiqvector), . - _C_LABEL(page0)
                     64:        subs    pc, lr, #4
                     65:        .org    .Lfiqvector + 0x100
                     66: #endif
                     67:
                     68: _C_LABEL(page0_data):
                     69: .Lreset_target:
                     70:        .word   reset_entry
                     71:
                     72: .Lundefined_target:
                     73:        .word   undefined_entry
                     74:
                     75: .Lswi_target:
                     76:        .word   swi_entry
                     77:
                     78: .Lprefetch_abort_target:
                     79:        .word   prefetch_abort_entry
                     80:
                     81: .Ldata_abort_target:
                     82:        .word   data_abort_entry
                     83:
                     84: .Laddress_exception_target:
                     85:        .word   address_exception_entry
                     86:
                     87: .Lirq_target:
                     88:        .word   irq_entry
                     89:
                     90: #ifdef __ARM_FIQ_INDIRECT
                     91: .Lfiq_target:
                     92:        .word   _C_LABEL(fiqvector)
                     93: #else
                     94:        .word   0       /* pad it out */
                     95: #endif
                     96: _C_LABEL(page0_end):
                     97:
                     98: #ifdef __ARM_FIQ_INDIRECT
                     99:        .data
                    100:        .align  0
                    101: _C_LABEL(fiqvector):
                    102:        subs    pc, lr, #4
                    103:        .org    _C_LABEL(fiqvector) + 0x100
                    104: #endif