Annotation of sys/arch/arm/arm/cpufunc_asm.S, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: cpufunc_asm.S,v 1.1 2004/02/01 05:09:48 drahn Exp $ */
! 2: /* $NetBSD: cpufunc_asm.S,v 1.12 2003/09/06 09:14:52 rearnsha Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1997,1998 Mark Brinicombe.
! 6: * Copyright (c) 1997 Causality Limited
! 7: * All rights reserved.
! 8: *
! 9: * Redistribution and use in source and binary forms, with or without
! 10: * modification, are permitted provided that the following conditions
! 11: * are met:
! 12: * 1. Redistributions of source code must retain the above copyright
! 13: * notice, this list of conditions and the following disclaimer.
! 14: * 2. Redistributions in binary form must reproduce the above copyright
! 15: * notice, this list of conditions and the following disclaimer in the
! 16: * documentation and/or other materials provided with the distribution.
! 17: * 3. All advertising materials mentioning features or use of this software
! 18: * must display the following acknowledgement:
! 19: * This product includes software developed by Causality Limited.
! 20: * 4. The name of Causality Limited may not be used to endorse or promote
! 21: * products derived from this software without specific prior written
! 22: * permission.
! 23: *
! 24: * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
! 25: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 26: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
! 27: * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
! 28: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 29: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 30: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 31: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 32: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 33: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 34: * SUCH DAMAGE.
! 35: *
! 36: * RiscBSD kernel project
! 37: *
! 38: * cpufunc.S
! 39: *
! 40: * Assembly functions for CPU / MMU / TLB specific operations
! 41: *
! 42: * Created : 30/01/97
! 43: */
! 44:
! 45: #include <machine/cpu.h>
! 46: #include <machine/asm.h>
! 47:
! 48: .text
! 49: .align 0
! 50:
! 51: ENTRY(cpufunc_nullop)
! 52: mov pc, lr
! 53:
! 54: /*
! 55: * Generic functions to read the internal coprocessor registers
! 56: *
! 57: * Currently these registers are :
! 58: * c0 - CPU ID
! 59: * c5 - Fault status
! 60: * c6 - Fault address
! 61: *
! 62: */
! 63:
! 64: ENTRY(cpufunc_id)
! 65: mrc p15, 0, r0, c0, c0, 0
! 66: mov pc, lr
! 67:
! 68: ENTRY(cpu_get_control)
! 69: mrc p15, 0, r0, c1, c0, 0
! 70: mov pc, lr
! 71:
! 72: ENTRY(cpu_read_cache_config)
! 73: mrc p15, 0, r0, c0, c0, 1
! 74: mov pc, lr
! 75:
! 76: ENTRY(cpufunc_faultstatus)
! 77: mrc p15, 0, r0, c5, c0, 0
! 78: mov pc, lr
! 79:
! 80: ENTRY(cpufunc_faultaddress)
! 81: mrc p15, 0, r0, c6, c0, 0
! 82: mov pc, lr
! 83:
! 84:
! 85: /*
! 86: * Generic functions to write the internal coprocessor registers
! 87: *
! 88: *
! 89: * Currently these registers are
! 90: * c1 - CPU Control
! 91: * c3 - Domain Access Control
! 92: *
! 93: * All other registers are CPU architecture specific
! 94: */
! 95:
! 96: #if 0 /* See below. */
! 97: ENTRY(cpufunc_control)
! 98: mcr p15, 0, r0, c1, c0, 0
! 99: mov pc, lr
! 100: #endif
! 101:
! 102: ENTRY(cpufunc_domains)
! 103: mcr p15, 0, r0, c3, c0, 0
! 104: mov pc, lr
! 105:
! 106: /*
! 107: * Generic functions to read/modify/write the internal coprocessor registers
! 108: *
! 109: *
! 110: * Currently these registers are
! 111: * c1 - CPU Control
! 112: *
! 113: * All other registers are CPU architecture specific
! 114: */
! 115:
! 116: ENTRY(cpufunc_control)
! 117: mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
! 118: bic r2, r3, r0 /* Clear bits */
! 119: eor r2, r2, r1 /* XOR bits */
! 120:
! 121: teq r2, r3 /* Only write if there is a change */
! 122: mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
! 123: mov r0, r3 /* Return old value */
! 124: mov pc, lr
! 125:
! 126: /*
! 127: * other potentially useful software functions are:
! 128: * clean D cache entry and flush I cache entry
! 129: * for the moment use cache_purgeID_E
! 130: */
! 131:
! 132: /* Random odd functions */
! 133:
! 134: /*
! 135: * Function to get the offset of a stored program counter from the
! 136: * instruction doing the store. This offset is defined to be the same
! 137: * for all STRs and STMs on a given implementation. Code based on
! 138: * section 2.4.3 of the ARM ARM (2nd Ed.), with modifications to work
! 139: * in 26-bit modes as well.
! 140: */
! 141: ENTRY(get_pc_str_offset)
! 142: mov ip, sp
! 143: stmfd sp!, {fp, ip, lr, pc}
! 144: sub fp, ip, #4
! 145: sub sp, sp, #4
! 146: mov r1, pc /* R1 = addr of following STR */
! 147: mov r0, r0
! 148: str pc, [sp] /* [SP] = . + offset */
! 149: ldr r0, [sp]
! 150: sub r0, r0, r1
! 151: ldmdb fp, {fp, sp, pc}
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