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1.1 ! nbrk 1: /* $OpenBSD: bus_space_asm_generic.S,v 1.1 2004/02/01 05:09:48 drahn Exp $ */
! 2: /* $NetBSD: bus_space_asm_generic.S,v 1.3 2003/03/27 19:46:14 mycroft Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1997 Causality Limited.
! 6: * Copyright (c) 1997 Mark Brinicombe.
! 7: * All rights reserved.
! 8: *
! 9: * Redistribution and use in source and binary forms, with or without
! 10: * modification, are permitted provided that the following conditions
! 11: * are met:
! 12: * 1. Redistributions of source code must retain the above copyright
! 13: * notice, this list of conditions and the following disclaimer.
! 14: * 2. Redistributions in binary form must reproduce the above copyright
! 15: * notice, this list of conditions and the following disclaimer in the
! 16: * documentation and/or other materials provided with the distribution.
! 17: * 3. All advertising materials mentioning features or use of this software
! 18: * must display the following acknowledgement:
! 19: * This product includes software developed by Mark Brinicombe
! 20: * for the NetBSD Project.
! 21: * 4. The name of the company nor the name of the author may be used to
! 22: * endorse or promote products derived from this software without specific
! 23: * prior written permission.
! 24: *
! 25: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
! 26: * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
! 27: * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 28: * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
! 29: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 30: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 31: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 32: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 33: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 34: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 35: * SUCH DAMAGE.
! 36: */
! 37:
! 38: #include <arm/asm.h>
! 39: #include <arm/cpuconf.h>
! 40:
! 41: /*
! 42: * Generic bus_space functions.
! 43: */
! 44:
! 45: /*
! 46: * read single
! 47: */
! 48:
! 49: ENTRY(generic_bs_r_1)
! 50: ldrb r0, [r1, r2]
! 51: mov pc, lr
! 52:
! 53: #if (ARM_ARCH_4 + ARM_ARCH_5) > 0
! 54: ENTRY(generic_armv4_bs_r_2)
! 55: ldrh r0, [r1, r2]
! 56: mov pc, lr
! 57: #endif
! 58:
! 59: ENTRY(generic_bs_r_4)
! 60: ldr r0, [r1, r2]
! 61: mov pc, lr
! 62:
! 63: /*
! 64: * write single
! 65: */
! 66:
! 67: ENTRY(generic_bs_w_1)
! 68: strb r3, [r1, r2]
! 69: mov pc, lr
! 70:
! 71: #if (ARM_ARCH_4 + ARM_ARCH_5) > 0
! 72: ENTRY(generic_armv4_bs_w_2)
! 73: strh r3, [r1, r2]
! 74: mov pc, lr
! 75: #endif
! 76:
! 77: ENTRY(generic_bs_w_4)
! 78: str r3, [r1, r2]
! 79: mov pc, lr
! 80:
! 81: /*
! 82: * read multiple
! 83: */
! 84:
! 85: ENTRY(generic_bs_rm_1)
! 86: add r0, r1, r2
! 87: mov r1, r3
! 88: ldr r2, [sp, #0]
! 89: teq r2, #0
! 90: moveq pc, lr
! 91:
! 92: 1: ldrb r3, [r0]
! 93: strb r3, [r1], #1
! 94: subs r2, r2, #1
! 95: bne 1b
! 96:
! 97: mov pc, lr
! 98:
! 99: #if (ARM_ARCH_4 + ARM_ARCH_5) > 0
! 100: ENTRY(generic_armv4_bs_rm_2)
! 101: add r0, r1, r2
! 102: mov r1, r3
! 103: ldr r2, [sp, #0]
! 104: teq r2, #0
! 105: moveq pc, lr
! 106:
! 107: 1: ldrh r3, [r0]
! 108: strh r3, [r1], #2
! 109: subs r2, r2, #1
! 110: bne 1b
! 111:
! 112: mov pc, lr
! 113: #endif
! 114:
! 115: ENTRY(generic_bs_rm_4)
! 116: add r0, r1, r2
! 117: mov r1, r3
! 118: ldr r2, [sp, #0]
! 119: teq r2, #0
! 120: moveq pc, lr
! 121:
! 122: 1: ldr r3, [r0]
! 123: str r3, [r1], #4
! 124: subs r2, r2, #1
! 125: bne 1b
! 126:
! 127: mov pc, lr
! 128:
! 129: /*
! 130: * write multiple
! 131: */
! 132:
! 133: ENTRY(generic_bs_wm_1)
! 134: add r0, r1, r2
! 135: mov r1, r3
! 136: ldr r2, [sp, #0]
! 137: teq r2, #0
! 138: moveq pc, lr
! 139:
! 140: 1: ldrb r3, [r1], #1
! 141: strb r3, [r0]
! 142: subs r2, r2, #1
! 143: bne 1b
! 144:
! 145: mov pc, lr
! 146:
! 147: #if (ARM_ARCH_4 + ARM_ARCH_5) > 0
! 148: ENTRY(generic_armv4_bs_wm_2)
! 149: add r0, r1, r2
! 150: mov r1, r3
! 151: ldr r2, [sp, #0]
! 152: teq r2, #0
! 153: moveq pc, lr
! 154:
! 155: 1: ldrh r3, [r1], #2
! 156: strh r3, [r0]
! 157: subs r2, r2, #1
! 158: bne 1b
! 159:
! 160: mov pc, lr
! 161: #endif
! 162:
! 163: ENTRY(generic_bs_wm_4)
! 164: add r0, r1, r2
! 165: mov r1, r3
! 166: ldr r2, [sp, #0]
! 167: teq r2, #0
! 168: moveq pc, lr
! 169:
! 170: 1: ldr r3, [r1], #4
! 171: str r3, [r0]
! 172: subs r2, r2, #1
! 173: bne 1b
! 174:
! 175: mov pc, lr
! 176:
! 177: /*
! 178: * read region
! 179: */
! 180:
! 181: ENTRY(generic_bs_rr_1)
! 182: add r0, r1, r2
! 183: mov r1, r3
! 184: ldr r2, [sp, #0]
! 185: teq r2, #0
! 186: moveq pc, lr
! 187:
! 188: 1: ldrb r3, [r0], #1
! 189: strb r3, [r1], #1
! 190: subs r2, r2, #1
! 191: bne 1b
! 192:
! 193: mov pc, lr
! 194:
! 195: #if (ARM_ARCH_4 + ARM_ARCH_5) > 0
! 196: ENTRY(generic_armv4_bs_rr_2)
! 197: add r0, r1, r2
! 198: mov r1, r3
! 199: ldr r2, [sp, #0]
! 200: teq r2, #0
! 201: moveq pc, lr
! 202:
! 203: 1: ldrh r3, [r0], #2
! 204: strh r3, [r1], #2
! 205: subs r2, r2, #1
! 206: bne 1b
! 207:
! 208: mov pc, lr
! 209: #endif
! 210:
! 211: ENTRY(generic_bs_rr_4)
! 212: add r0, r1, r2
! 213: mov r1, r3
! 214: ldr r2, [sp, #0]
! 215: teq r2, #0
! 216: moveq pc, lr
! 217:
! 218: 1: ldr r3, [r0], #4
! 219: str r3, [r1], #4
! 220: subs r2, r2, #1
! 221: bne 1b
! 222:
! 223: mov pc, lr
! 224:
! 225: /*
! 226: * write region.
! 227: */
! 228:
! 229: ENTRY(generic_bs_wr_1)
! 230: add r0, r1, r2
! 231: mov r1, r3
! 232: ldr r2, [sp, #0]
! 233: teq r2, #0
! 234: moveq pc, lr
! 235:
! 236: 1: ldrb r3, [r1], #1
! 237: strb r3, [r0], #1
! 238: subs r2, r2, #1
! 239: bne 1b
! 240:
! 241: mov pc, lr
! 242:
! 243: #if (ARM_ARCH_4 + ARM_ARCH_5) > 0
! 244: ENTRY(generic_armv4_bs_wr_2)
! 245: add r0, r1, r2
! 246: mov r1, r3
! 247: ldr r2, [sp, #0]
! 248: teq r2, #0
! 249: moveq pc, lr
! 250:
! 251: 1: ldrh r3, [r1], #2
! 252: strh r3, [r0], #2
! 253: subs r2, r2, #1
! 254: bne 1b
! 255:
! 256: mov pc, lr
! 257: #endif
! 258:
! 259: ENTRY(generic_bs_wr_4)
! 260: add r0, r1, r2
! 261: mov r1, r3
! 262: ldr r2, [sp, #0]
! 263: teq r2, #0
! 264: moveq pc, lr
! 265:
! 266: 1: ldr r3, [r1], #4
! 267: str r3, [r0], #4
! 268: subs r2, r2, #1
! 269: bne 1b
! 270:
! 271: mov pc, lr
! 272:
! 273: /*
! 274: * set region
! 275: */
! 276:
! 277: ENTRY(generic_bs_sr_1)
! 278: add r0, r1, r2
! 279: mov r1, r3
! 280: ldr r2, [sp, #0]
! 281: teq r2, #0
! 282: moveq pc, lr
! 283:
! 284: 1: strb r1, [r0], #1
! 285: subs r2, r2, #1
! 286: bne 1b
! 287:
! 288: mov pc, lr
! 289:
! 290: #if (ARM_ARCH_4 + ARM_ARCH_5) > 0
! 291: ENTRY(generic_armv4_bs_sr_2)
! 292: add r0, r1, r2
! 293: mov r1, r3
! 294: ldr r2, [sp, #0]
! 295: teq r2, #0
! 296: moveq pc, lr
! 297:
! 298: 1: strh r1, [r0], #2
! 299: subs r2, r2, #1
! 300: bne 1b
! 301:
! 302: mov pc, lr
! 303: #endif
! 304:
! 305: ENTRY(generic_bs_sr_4)
! 306: add r0, r1, r2
! 307: mov r1, r3
! 308: ldr r2, [sp, #0]
! 309: teq r2, #0
! 310: moveq pc, lr
! 311:
! 312: 1: str r1, [r0], #4
! 313: subs r2, r2, #1
! 314: bne 1b
! 315:
! 316: mov pc, lr
! 317:
! 318: /*
! 319: * copy region
! 320: */
! 321:
! 322: #if (ARM_ARCH_4 + ARM_ARCH_5) > 0
! 323: ENTRY(generic_armv4_bs_c_2)
! 324: add r0, r1, r2
! 325: ldr r2, [sp, #0]
! 326: add r1, r2, r3
! 327: ldr r2, [sp, #4]
! 328: teq r2, #0
! 329: moveq pc, lr
! 330:
! 331: cmp r0, r1
! 332: blt 2f
! 333:
! 334: 1: ldrh r3, [r0], #2
! 335: strh r3, [r1], #2
! 336: subs r2, r2, #1
! 337: bne 1b
! 338:
! 339: mov pc, lr
! 340:
! 341: 2: add r0, r0, r2, lsl #1
! 342: add r1, r1, r2, lsl #1
! 343: sub r0, r0, #2
! 344: sub r1, r1, #2
! 345:
! 346: 3: ldrh r3, [r0], #-2
! 347: strh r3, [r1], #-2
! 348: subs r2, r2, #1
! 349: bne 3b
! 350:
! 351: mov pc, lr
! 352: #endif