Annotation of sys/arch/arm/arm/ast.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ast.c,v 1.8 2007/05/14 07:07:09 art Exp $ */
2: /* $NetBSD: ast.c,v 1.6 2003/10/31 16:44:34 cl Exp $ */
3:
4: /*
5: * Copyright (c) 1994,1995 Mark Brinicombe
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by the RiscBSD team.
19: * 4. The name of the company nor the name of the author may be used to
20: * endorse or promote products derived from this software without specific
21: * prior written permission.
22: *
23: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
24: * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25: * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26: * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
27: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33: * SUCH DAMAGE.
34: *
35: * RiscBSD kernel project
36: *
37: * ast.c
38: *
39: * Code to handle ast's and returns to user mode
40: *
41: * Created : 11/10/94
42: */
43:
44: #include <sys/param.h>
45: #include <sys/proc.h>
46: #include <sys/user.h>
47: #include <sys/acct.h>
48: #include <sys/systm.h>
49: #include <sys/kernel.h>
50: #include <sys/signal.h>
51: #include <sys/signalvar.h>
52: #include <sys/vmmeter.h>
53:
54: #include <machine/cpu.h>
55: #include <machine/frame.h>
56: #include <machine/cpu.h>
57:
58: #include <arm/cpufunc.h>
59:
60: #include <uvm/uvm_extern.h>
61:
62: #ifdef acorn26
63: #include <machine/machdep.h>
64: #endif
65:
66: /*
67: * Prototypes
68: */
69: void ast(struct trapframe *);
70:
71: int want_resched;
72: extern int astpending;
73:
74: void
75: userret(struct proc *p)
76: {
77: int sig;
78:
79: /* Take pending signals. */
80: while ((sig = (CURSIG(p))) != 0)
81: postsig(sig);
82:
83: p->p_cpu->ci_schedstate.spc_curpriority = p->p_priority = p->p_usrpri;
84: }
85:
86:
87: /*
88: * Handle asynchronous system traps.
89: * This is called from the irq handler to deliver signals
90: * and switch processes if required.
91: */
92:
93: void
94: ast(struct trapframe *tf)
95: {
96: struct proc *p = curproc;
97:
98: #ifdef acorn26
99: /* Enable interrupts if they were enabled before the trap. */
100: if ((tf->tf_r15 & R15_IRQ_DISABLE) == 0)
101: int_on();
102: #else
103: /* Interrupts were restored by exception_exit. */
104: #endif
105:
106: uvmexp.traps++;
107: uvmexp.softs++;
108:
109: #ifdef DEBUG
110: if (p == NULL)
111: panic("ast: no curproc!");
112: if (&p->p_addr->u_pcb == 0)
113: panic("ast: no pcb!");
114: #endif
115:
116: if (p->p_flag & P_OWEUPC) {
117: ADDUPROF(p);
118: }
119:
120: /* Allow a forced task switch. */
121: if (want_resched)
122: preempt(NULL);
123:
124: userret(p);
125: }
126:
127: /* End of ast.c */
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