Annotation of sys/arch/amd64/include/pte.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: pte.h,v 1.5 2006/10/16 15:51:26 tom Exp $ */
2: /* $NetBSD: pte.h,v 1.1 2003/04/26 18:39:47 fvdl Exp $ */
3:
4: /*
5: * Copyright (c) 2001 Wasabi Systems, Inc.
6: * All rights reserved.
7: *
8: * Written by Frank van der Linden for Wasabi Systems, Inc.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed for the NetBSD Project by
21: * Wasabi Systems, Inc.
22: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23: * or promote products derived from this software without specific prior
24: * written permission.
25: *
26: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36: * POSSIBILITY OF SUCH DAMAGE.
37: */
38:
39: #ifndef _AMD64_PTE_H_
40: #define _AMD64_PTE_H_
41:
42: /*
43: * amd64 MMU hardware structure:
44: *
45: * the (first generation) amd64 MMU is a 4-level MMU which maps 2^48 bytes
46: * of virtual memory. The pagesize we use is 4K (4096 [0x1000] bytes),
47: * although 2M and 4M can be used as well. The indexes in the levels
48: * are 9 bits wide (512 64bit entries per level), dividing the bits
49: * 9-9-9-9-12.
50: *
51: * The top level table, called PML4, contains 512 64bit entries pointing
52: * to 3rd level table. The 3rd level table is called the 'page directory
53: * pointers directory' and has 512 entries pointing to page directories.
54: * The 2nd level is the page directory, containing 512 pointers to
55: * page table pages. Lastly, level 1 consists of pages containing 512
56: * PTEs.
57: *
58: * Simply put, levels 4-1 all consist of pages containing 512
59: * entries pointing to the next level. Level 0 is the actual PTEs
60: * themselves.
61: *
62: * For a description on the other bits, which are i386 compatible,
63: * see the i386 pte.h
64: */
65:
66: #if !defined(_LOCORE)
67:
68: /*
69: * here we define the data types for PDEs and PTEs
70: */
71:
72: typedef u_int64_t pd_entry_t; /* PDE */
73: typedef u_int64_t pt_entry_t; /* PTE */
74:
75: #endif
76:
77: /*
78: * now we define various for playing with virtual addresses
79: */
80:
81: #define L1_SHIFT 12
82: #define L2_SHIFT 21
83: #define L3_SHIFT 30
84: #define L4_SHIFT 39
85: #define NBPD_L1 (1ULL << L1_SHIFT) /* # bytes mapped by L1 ent (4K) */
86: #define NBPD_L2 (1ULL << L2_SHIFT) /* # bytes mapped by L2 ent (2MB) */
87: #define NBPD_L3 (1ULL << L3_SHIFT) /* # bytes mapped by L3 ent (1G) */
88: #define NBPD_L4 (1ULL << L4_SHIFT) /* # bytes mapped by L4 ent (512G) */
89:
90: #define L4_MASK 0x0000ff8000000000UL
91: #define L3_MASK 0x0000007fc0000000UL
92: #define L2_MASK 0x000000003fe00000UL
93: #define L1_MASK 0x00000000001ff000UL
94:
95: #define L4_FRAME L4_MASK
96: #define L3_FRAME (L4_FRAME|L3_MASK)
97: #define L2_FRAME (L3_FRAME|L2_MASK)
98: #define L1_FRAME (L2_FRAME|L1_MASK)
99:
100: /*
101: * PDE/PTE bits. These are no different from their i386 counterparts.
102: */
103:
104: #define PG_V 0x0000000000000001UL /* valid */
105: #define PG_RO 0x0000000000000000UL /* read-only */
106: #define PG_RW 0x0000000000000002UL /* read-write */
107: #define PG_u 0x0000000000000004UL /* user accessible */
108: #define PG_PROT 0x0000000000000006UL
109: #define PG_N 0x0000000000000018UL /* non-cacheable */
110: #define PG_U 0x0000000000000020UL /* used */
111: #define PG_M 0x0000000000000040UL /* modified */
112: #define PG_PS 0x0000000000000080UL /* 2MB page size */
113: #define PG_G 0x0000000000000100UL /* not flushed */
114: #define PG_AVAIL1 0x0000000000000200UL
115: #define PG_AVAIL2 0x0000000000000400UL
116: #define PG_AVAIL3 0x0000000000000800UL
117: #define PG_NX 0x8000000000000000UL /* non-executable */
118: #define PG_FRAME 0x000ffffffffff000UL
119:
120: #define PG_LGFRAME 0x000fffffffc00000UL /* large (2M) page frame mask */
121:
122: /*
123: * short forms of protection codes
124: */
125:
126: #define PG_KR 0x0000000000000000UL /* kernel read-only */
127: #define PG_KW 0x0000000000000002UL /* kernel read-write */
128:
129: /*
130: * page protection exception bits
131: */
132:
133: #define PGEX_P 0x01 /* protection violation (vs. no mapping) */
134: #define PGEX_W 0x02 /* exception during a write cycle */
135: #define PGEX_U 0x04 /* exception while in user mode (upl) */
136: #define PGEX_I 0x10 /* instruction fetch blocked by NX */
137:
138: #endif /* _AMD64_PTE_H_ */
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