Annotation of sys/arch/amd64/include/i82093reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: i82093reg.h,v 1.2 2004/06/25 11:03:28 art Exp $ */
2: /* $NetBSD: i82093reg.h,v 1.1 2003/02/26 21:26:10 fvdl Exp $ */
3:
4: /*-
5: * Copyright (c) 2000 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by RedBack Networks Inc.
10: *
11: * Author: Bill Sommerfeld
12: *
13: * Redistribution and use in source and binary forms, with or without
14: * modification, are permitted provided that the following conditions
15: * are met:
16: * 1. Redistributions of source code must retain the above copyright
17: * notice, this list of conditions and the following disclaimer.
18: * 2. Redistributions in binary form must reproduce the above copyright
19: * notice, this list of conditions and the following disclaimer in the
20: * documentation and/or other materials provided with the distribution.
21: * 3. All advertising materials mentioning features or use of this software
22: * must display the following acknowledgement:
23: * This product includes software developed by the NetBSD
24: * Foundation, Inc. and its contributors.
25: * 4. Neither the name of The NetBSD Foundation nor the names of its
26: * contributors may be used to endorse or promote products derived
27: * from this software without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
30: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
32: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
33: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39: * POSSIBILITY OF SUCH DAMAGE.
40: */
41:
42: /*
43: * Typically, the first apic lives here.
44: */
45: #define IOAPIC_BASE_DEFAULT 0xfec00000
46:
47: /*
48: * Memory-space registers.
49: */
50:
51: /*
52: * The externally visible registers are all 32 bits wide;
53: * store the register number of interest in IOAPIC_REG, and store/fetch
54: * the real value in IOAPIC_DATA.
55: */
56:
57:
58:
59: #define IOAPIC_REG 0x0000
60: #define IOAPIC_DATA 0x0010
61:
62: /*
63: * Internal I/O APIC registers.
64: */
65:
66: #define IOAPIC_ID 0x00
67:
68: #define IOAPIC_ID_SHIFT 24
69: #define IOAPIC_ID_MASK 0x0f000000
70:
71: /* Version, and maximum interrupt pin number. */
72:
73: #define IOAPIC_VER 0x01
74:
75: #define IOAPIC_VER_SHIFT 0
76: #define IOAPIC_VER_MASK 0x000000ff
77:
78: #define IOAPIC_MAX_SHIFT 16
79: #define IOAPIC_MAX_MASK 0x00ff0000
80:
81: /*
82: * Arbitration ID. Same format as IOAPIC_ID register.
83: */
84: #define IOAPIC_ARB 0x02
85:
86: /*
87: * Redirection table registers.
88: */
89:
90: #define IOAPIC_REDHI(pin) (0x11 + ((pin)<<1))
91: #define IOAPIC_REDLO(pin) (0x10 + ((pin)<<1))
92:
93: #define IOAPIC_REDHI_DEST_SHIFT 24 /* destination. */
94: #define IOAPIC_REDHI_DEST_MASK 0xff000000
95:
96: #define IOAPIC_REDLO_MASK 0x00010000 /* 0=enabled; 1=masked */
97:
98: #define IOAPIC_REDLO_LEVEL 0x00008000 /* 0=edge, 1=level */
99: #define IOAPIC_REDLO_RIRR 0x00004000 /* remote IRR; read only */
100: #define IOAPIC_REDLO_ACTLO 0x00002000 /* 0=act. hi; 1=act. lo */
101: #define IOAPIC_REDLO_DELSTS 0x00001000 /* 0=idle; 1=send pending */
102: #define IOAPIC_REDLO_DSTMOD 0x00000800 /* 0=physical; 1=logical */
103:
104: #define IOAPIC_REDLO_DEL_MASK 0x00000700 /* del. mode mask */
105: #define IOAPIC_REDLO_DEL_SHIFT 8
106:
107: #define IOAPIC_REDLO_DEL_FIXED 0
108: #define IOAPIC_REDLO_DEL_LOPRI 1
109: #define IOAPIC_REDLO_DEL_SMI 2
110: #define IOAPIC_REDLO_DEL_NMI 4
111: #define IOAPIC_REDLO_DEL_INIT 5
112: #define IOAPIC_REDLO_DEL_EXTINT 7
113:
114: #define IOAPIC_REDLO_VECTOR_MASK 0x000000ff /* delivery vector */
115:
116: #define IMCR_ADDR 0x22
117: #define IMCR_DATA 0x23
118:
119: #define IMCR_REGISTER 0x70
120: #define IMCR_PIC 0x00
121: #define IMCR_APIC 0x01
122:
123: #ifdef _KERNEL
124:
125: #define ioapic_asm_ack(num) \
126: movl $0,(_C_LABEL(local_apic)+LAPIC_EOI)(%rip)
127:
128: #ifdef MULTIPROCESSOR
129:
130: #ifdef notyet
131: #define ioapic_asm_lock(num) \
132: movl $1,%esi ;\
133: 77: \
134: xchgl %esi,PIC_LOCK(%rdi) ;\
135: testl %esi,%esi ;\
136: jne 77b
137:
138: #define ioapic_asm_unlock(num) \
139: movl $0,PIC_LOCK(%rdi)
140: #else
141: #define ioapic_asm_lock(num)
142: #define ioapic_asm_unlock(num)
143: #endif
144:
145: #else
146:
147: #define ioapic_asm_lock(num)
148: #define ioapic_asm_unlock(num)
149:
150: #endif /* MULTIPROCESSOR */
151:
152:
153: #define ioapic_mask(num) \
154: movq IS_PIC(%r14),%rdi ;\
155: ioapic_asm_lock(num) ;\
156: movl IS_PIN(%r14),%esi ;\
157: leaq 0x10(%rsi,%rsi,1),%rsi ;\
158: movq IOAPIC_SC_REG(%rdi),%r15 ;\
159: movl %esi, (%r15) ;\
160: movq IOAPIC_SC_DATA(%rdi),%r15 ;\
161: movl (%r15),%esi ;\
162: orl $IOAPIC_REDLO_MASK,%esi ;\
163: movl %esi,(%r15) ;\
164: ioapic_asm_unlock(num)
165:
166: #define ioapic_unmask(num) \
167: cmpq $IREENT_MAGIC,(TF_ERR+8)(%rsp) ;\
168: jne 79f ;\
169: movq IS_PIC(%r14),%rdi ;\
170: ioapic_asm_lock(num) ;\
171: movl IS_PIN(%r14),%esi ;\
172: leaq 0x10(%rsi,%rsi,1),%rsi ;\
173: movq IOAPIC_SC_REG(%rdi),%r15 ;\
174: movq IOAPIC_SC_DATA(%rdi),%r13 ;\
175: movl %esi, (%r15) ;\
176: movl (%r13),%r12d ;\
177: andl $~IOAPIC_REDLO_MASK,%r12d ;\
178: movl %esi,(%r15) ;\
179: movl %r12d,(%r13) ;\
180: ioapic_asm_unlock(num) ;\
181: 79:
182:
183: #endif
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