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File: [local] / sys / arch / amd64 / include / cacheinfo.h (download)
Revision 1.1.1.1 (vendor branch), Tue Mar 4 16:05:05 2008 UTC (16 years, 3 months ago) by nbrk
Import of OpenBSD 4.2 release kernel tree with initial code to support Jornada 720/728, StrongARM 1110-based handheld PC. At this point kernel roots on NFS and boots into vfs_mountroot() and traps. What is supported: - glass console, Jornada framebuffer (jfb) works in 16bpp direct color mode (needs some palette tweaks for non black/white/blue colors, i think) - saic, SA11x0 interrupt controller (needs cleanup) - sacom, SA11x0 UART (supported only as boot console for now) - SA11x0 GPIO controller fully supported (but can't handle multiple interrupt handlers on one gpio pin) - sassp, SSP port on SA11x0 that attaches spibus - Jornada microcontroller (jmcu) to control kbd, battery, etc throught the SPI bus (wskbd attaches on jmcu, but not tested) - tod functions seem work - initial code for SA-1111 (chip companion) : this is TODO Next important steps, i think: - gpio and intc on sa1111 - pcmcia support for sa11x0 (and sa1111 help logic) - REAL root on nfs when we have PCMCIA support (we may use any of supported pccard NICs) - root on wd0! (using already supported PCMCIA-ATA) |
/* $OpenBSD: cacheinfo.h,v 1.1 2004/01/28 01:39:39 mickey Exp $ */ /* $NetBSD: cacheinfo.h,v 1.1 2003/04/25 21:54:30 fvdl Exp $ */ #ifndef _X86_CACHEINFO_H #define _X86_CACHEINFO_H struct x86_cache_info { uint8_t cai_index; uint8_t cai_desc; uint8_t cai_associativity; u_int cai_totalsize; /* #entries for TLB, bytes for cache */ u_int cai_linesize; /* or page size for TLB */ const char *cai_string; }; #define CAI_ITLB 0 /* Instruction TLB (4K pages) */ #define CAI_ITLB2 1 /* Instruction TLB (2/4M pages) */ #define CAI_DTLB 2 /* Data TLB (4K pages) */ #define CAI_DTLB2 3 /* Data TLB (2/4M pages) */ #define CAI_ICACHE 4 /* Instruction cache */ #define CAI_DCACHE 5 /* Data cache */ #define CAI_L2CACHE 6 /* Level 2 cache */ #define CAI_COUNT 7 struct cpu_info; const struct x86_cache_info *cache_info_lookup(const struct x86_cache_info *, u_int8_t); void amd_cpu_cacheinfo(struct cpu_info *); void x86_print_cacheinfo(struct cpu_info *); /* * AMD Cache Info: * * Athlon, Duron: * * Function 8000.0005 L1 TLB/Cache Information * EAX -- L1 TLB 2/4MB pages * EBX -- L1 TLB 4K pages * ECX -- L1 D-cache * EDX -- L1 I-cache * * Function 8000.0006 L2 TLB/Cache Information * EAX -- L2 TLB 2/4MB pages * EBX -- L2 TLB 4K pages * ECX -- L2 Unified cache * EDX -- reserved * * K5, K6: * * Function 8000.0005 L1 TLB/Cache Information * EAX -- reserved * EBX -- TLB 4K pages * ECX -- L1 D-cache * EDX -- L1 I-cache * * K6-III: * * Function 8000.0006 L2 Cache Information * EAX -- reserved * EBX -- reserved * ECX -- L2 Unified cache * EDX -- reserved */ /* L1 TLB 2/4MB pages */ #define AMD_L1_EAX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) #define AMD_L1_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) #define AMD_L1_EAX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) #define AMD_L1_EAX_ITLB_ENTRIES(x) ( (x) & 0xff) /* L1 TLB 4K pages */ #define AMD_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) #define AMD_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) #define AMD_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) #define AMD_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff) /* L1 Data Cache */ #define AMD_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) #define AMD_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff) #define AMD_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff) #define AMD_L1_ECX_DC_LS(x) ( (x) & 0xff) /* L1 Instruction Cache */ #define AMD_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) #define AMD_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff) #define AMD_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff) #define AMD_L1_EDX_IC_LS(x) ( (x) & 0xff) /* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */ /* L2 TLB 2/4MB pages */ #define AMD_L2_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf) #define AMD_L2_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff) #define AMD_L2_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) #define AMD_L2_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff) /* L2 TLB 4K pages */ #define AMD_L2_EBX_DTLB_ASSOC(x) (((x) >> 28) & 0xf) #define AMD_L2_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff) #define AMD_L2_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) #define AMD_L2_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff) /* L2 Cache */ #define AMD_L2_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024) #define AMD_L2_ECX_C_ASSOC(x) (((x) >> 12) & 0xf) #define AMD_L2_ECX_C_LPT(x) (((x) >> 8) & 0xf) #define AMD_L2_ECX_C_LS(x) ( (x) & 0xff) #endif /* _X86_CACHEINFO_H */