Annotation of sys/arch/amd64/include/cacheinfo.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: cacheinfo.h,v 1.1 2004/01/28 01:39:39 mickey Exp $ */
! 2: /* $NetBSD: cacheinfo.h,v 1.1 2003/04/25 21:54:30 fvdl Exp $ */
! 3:
! 4: #ifndef _X86_CACHEINFO_H
! 5: #define _X86_CACHEINFO_H
! 6:
! 7: struct x86_cache_info {
! 8: uint8_t cai_index;
! 9: uint8_t cai_desc;
! 10: uint8_t cai_associativity;
! 11: u_int cai_totalsize; /* #entries for TLB, bytes for cache */
! 12: u_int cai_linesize; /* or page size for TLB */
! 13: const char *cai_string;
! 14: };
! 15:
! 16: #define CAI_ITLB 0 /* Instruction TLB (4K pages) */
! 17: #define CAI_ITLB2 1 /* Instruction TLB (2/4M pages) */
! 18: #define CAI_DTLB 2 /* Data TLB (4K pages) */
! 19: #define CAI_DTLB2 3 /* Data TLB (2/4M pages) */
! 20: #define CAI_ICACHE 4 /* Instruction cache */
! 21: #define CAI_DCACHE 5 /* Data cache */
! 22: #define CAI_L2CACHE 6 /* Level 2 cache */
! 23:
! 24: #define CAI_COUNT 7
! 25:
! 26: struct cpu_info;
! 27:
! 28: const struct x86_cache_info *cache_info_lookup(const struct x86_cache_info *,
! 29: u_int8_t);
! 30: void amd_cpu_cacheinfo(struct cpu_info *);
! 31: void x86_print_cacheinfo(struct cpu_info *);
! 32:
! 33: /*
! 34: * AMD Cache Info:
! 35: *
! 36: * Athlon, Duron:
! 37: *
! 38: * Function 8000.0005 L1 TLB/Cache Information
! 39: * EAX -- L1 TLB 2/4MB pages
! 40: * EBX -- L1 TLB 4K pages
! 41: * ECX -- L1 D-cache
! 42: * EDX -- L1 I-cache
! 43: *
! 44: * Function 8000.0006 L2 TLB/Cache Information
! 45: * EAX -- L2 TLB 2/4MB pages
! 46: * EBX -- L2 TLB 4K pages
! 47: * ECX -- L2 Unified cache
! 48: * EDX -- reserved
! 49: *
! 50: * K5, K6:
! 51: *
! 52: * Function 8000.0005 L1 TLB/Cache Information
! 53: * EAX -- reserved
! 54: * EBX -- TLB 4K pages
! 55: * ECX -- L1 D-cache
! 56: * EDX -- L1 I-cache
! 57: *
! 58: * K6-III:
! 59: *
! 60: * Function 8000.0006 L2 Cache Information
! 61: * EAX -- reserved
! 62: * EBX -- reserved
! 63: * ECX -- L2 Unified cache
! 64: * EDX -- reserved
! 65: */
! 66:
! 67: /* L1 TLB 2/4MB pages */
! 68: #define AMD_L1_EAX_DTLB_ASSOC(x) (((x) >> 24) & 0xff)
! 69: #define AMD_L1_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff)
! 70: #define AMD_L1_EAX_ITLB_ASSOC(x) (((x) >> 8) & 0xff)
! 71: #define AMD_L1_EAX_ITLB_ENTRIES(x) ( (x) & 0xff)
! 72:
! 73: /* L1 TLB 4K pages */
! 74: #define AMD_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff)
! 75: #define AMD_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff)
! 76: #define AMD_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff)
! 77: #define AMD_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff)
! 78:
! 79: /* L1 Data Cache */
! 80: #define AMD_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
! 81: #define AMD_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff)
! 82: #define AMD_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff)
! 83: #define AMD_L1_ECX_DC_LS(x) ( (x) & 0xff)
! 84:
! 85: /* L1 Instruction Cache */
! 86: #define AMD_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
! 87: #define AMD_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff)
! 88: #define AMD_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff)
! 89: #define AMD_L1_EDX_IC_LS(x) ( (x) & 0xff)
! 90:
! 91: /* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */
! 92:
! 93: /* L2 TLB 2/4MB pages */
! 94: #define AMD_L2_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf)
! 95: #define AMD_L2_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff)
! 96: #define AMD_L2_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf)
! 97: #define AMD_L2_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff)
! 98:
! 99: /* L2 TLB 4K pages */
! 100: #define AMD_L2_EBX_DTLB_ASSOC(x) (((x) >> 28) & 0xf)
! 101: #define AMD_L2_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff)
! 102: #define AMD_L2_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf)
! 103: #define AMD_L2_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff)
! 104:
! 105: /* L2 Cache */
! 106: #define AMD_L2_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024)
! 107: #define AMD_L2_ECX_C_ASSOC(x) (((x) >> 12) & 0xf)
! 108: #define AMD_L2_ECX_C_LPT(x) (((x) >> 8) & 0xf)
! 109: #define AMD_L2_ECX_C_LS(x) ( (x) & 0xff)
! 110:
! 111: #endif /* _X86_CACHEINFO_H */
CVSweb