Annotation of sys/arch/alpha/tc/sccreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: sccreg.h,v 1.5 2003/06/02 23:27:44 millert Exp $ */
! 2: /* $NetBSD: sccreg.h,v 1.3 1997/04/06 22:30:30 cgd Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University
! 6: * All Rights Reserved.
! 7: *
! 8: * Permission to use, copy, modify and distribute this software and its
! 9: * documentation is hereby granted, provided that both the copyright
! 10: * notice and this permission notice appear in all copies of the
! 11: * software, derivative works or modified versions, and any portions
! 12: * thereof, and that both notices appear in supporting documentation.
! 13: *
! 14: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
! 15: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
! 16: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
! 17: *
! 18: * Carnegie Mellon requests users of this software to return to
! 19: *
! 20: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
! 21: * School of Computer Science
! 22: * Carnegie Mellon University
! 23: * Pittsburgh PA 15213-3890
! 24: *
! 25: * any improvements or extensions that they make and grant Carnegie Mellon
! 26: * the rights to redistribute these changes.
! 27: */
! 28:
! 29: /*-
! 30: * Copyright (c) 1992, 1993
! 31: * The Regents of the University of California. All rights reserved.
! 32: *
! 33: * This code is derived from software contributed to Berkeley by
! 34: * Ralph Campbell and Rick Macklem.
! 35: *
! 36: * Redistribution and use in source and binary forms, with or without
! 37: * modification, are permitted provided that the following conditions
! 38: * are met:
! 39: * 1. Redistributions of source code must retain the above copyright
! 40: * notice, this list of conditions and the following disclaimer.
! 41: * 2. Redistributions in binary form must reproduce the above copyright
! 42: * notice, this list of conditions and the following disclaimer in the
! 43: * documentation and/or other materials provided with the distribution.
! 44: * 3. Neither the name of the University nor the names of its contributors
! 45: * may be used to endorse or promote products derived from this software
! 46: * without specific prior written permission.
! 47: *
! 48: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 49: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 50: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 51: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 52: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 53: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 54: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 55: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 56: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 57: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 58: * SUCH DAMAGE.
! 59: *
! 60: * @(#)sccreg.h 8.1 (Berkeley) 6/10/93
! 61: */
! 62:
! 63: /*
! 64: * Definitions for Intel 82530 serial communications chip. Each chip is a
! 65: * dual uart with the A channels used for the keyboard and mouse with the B
! 66: * channel(s) for comm ports with modem control. Since some registers are
! 67: * used for the other channel, the following macros are used to access the
! 68: * register ports.
! 69: *
! 70: * Actual access to the registers is provided by sccvar.h, as it's
! 71: * machine-dependent.
! 72: */
! 73:
! 74: /* Scc channel numbers; B channel comes first. */
! 75: #define SCC_CHANNEL_B 0
! 76: #define SCC_CHANNEL_A 1
! 77:
! 78: #define SCC_INIT_REG(scc, chan) { \
! 79: char tmp; \
! 80: scc_get_datum((scc)->scc_channel[(chan)].scc_command, tmp); \
! 81: scc_get_datum((scc)->scc_channel[(chan)].scc_command, tmp); \
! 82: }
! 83:
! 84: #define SCC_READ_REG(scc, chan, reg, val) { \
! 85: scc_set_datum((scc)->scc_channel[(chan)].scc_command, reg); \
! 86: scc_get_datum((scc)->scc_channel[(chan)].scc_command, val); \
! 87: }
! 88:
! 89: #define SCC_READ_REG_ZERO(scc, chan, val) { \
! 90: scc_get_datum((scc)->scc_channel[(chan)].scc_command, val); \
! 91: }
! 92:
! 93: #define SCC_WRITE_REG(scc, chan, reg, val) { \
! 94: scc_set_datum((scc)->scc_channel[(chan)].scc_command, reg); \
! 95: scc_set_datum((scc)->scc_channel[(chan)].scc_command, val); \
! 96: }
! 97:
! 98: #define SCC_WRITE_REG_ZERO(scc, chan, val) { \
! 99: scc_set_datum((scc)->scc_channel[(chan)].scc_command, val); \
! 100: }
! 101:
! 102: #define SCC_READ_DATA(scc, chan, val) { \
! 103: scc_get_datum((scc)->scc_channel[(chan)].scc_data, val); \
! 104: }
! 105:
! 106: #define SCC_WRITE_DATA(scc, chan, val) { \
! 107: scc_set_datum((scc)->scc_channel[(chan)].scc_data, val); \
! 108: }
! 109:
! 110: /* Addressable registers. */
! 111: #define SCC_RR0 0 /* status register */
! 112: #define SCC_RR1 1 /* special receive conditions */
! 113: #define SCC_RR8 8 /* recv buffer (alias for data) */
! 114: #define SCC_RR10 10 /* sdlc status */
! 115: #define SCC_RR15 15 /* interrupts currently enabled */
! 116:
! 117: #define SCC_WR0 0 /* reg select, and commands */
! 118: #define SCC_WR1 1 /* interrupt and DMA enables */
! 119: #define SCC_WR3 3 /* receiver params and enables */
! 120: #define SCC_WR4 4 /* clock/char/parity params */
! 121: #define SCC_WR5 5 /* xmit params and enables */
! 122: #define SCC_WR8 8 /* xmit buffer (alias for data) */
! 123: #define SCC_WR9 9 /* vectoring and resets */
! 124: #define SCC_WR10 10 /* synchr params */
! 125: #define SCC_WR11 11 /* clocking definitions */
! 126: #define SCC_WR14 14 /* BRG enables and commands */
! 127: #define SCC_WR15 15 /* interrupt enables */
! 128:
! 129: /* Read register's defines. */
! 130:
! 131: /*
! 132: * RR2 contains the interrupt vector unmodified (channel A) or
! 133: * modified as follows (channel B, if vector-include-status).
! 134: */
! 135: #define SCC_RR2_STATUS(val) ((val)&0xf)
! 136:
! 137: #define SCC_RR2_B_XMIT_DONE 0x0
! 138: #define SCC_RR2_B_EXT_STATUS 0x2
! 139: #define SCC_RR2_B_RECV_DONE 0x4
! 140: #define SCC_RR2_B_RECV_SPECIAL 0x6
! 141: #define SCC_RR2_A_XMIT_DONE 0x8
! 142: #define SCC_RR2_A_EXT_STATUS 0xa
! 143: #define SCC_RR2_A_RECV_DONE 0xc
! 144: #define SCC_RR2_A_RECV_SPECIAL 0xe
! 145:
! 146: /* RR12/RR13 hold the timing base, upper byte in RR13. */
! 147: #define SCC_GET_TIMING_BASE(scc, chan, val) { \
! 148: register char tmp; \
! 149: SCC_READ_REG(scc, chan, ZSRR_BAUDLO, val); \
! 150: SCC_READ_REG(scc, chan, ZSRR_BAUDHI, tmp); \
! 151: (val) = ((val) << 8) | (tmp & 0xff); \
! 152: }
! 153:
! 154: /*
! 155: * Write register's defines.
! 156: */
! 157:
! 158: /* WR12/WR13 are for timing base preset */
! 159: #define SCC_SET_TIMING_BASE(scc, chan, val) { \
! 160: SCC_WRITE_REG(scc, chan, ZSWR_BAUDLO, val); \
! 161: SCC_WRITE_REG(scc, chan, ZSWR_BAUDHI, (val) >> 8); \
! 162: }
! 163:
! 164: /* Bits in dm lsr, copied from dmreg.h. */
! 165: #define DML_DSR 0000400 /* data set ready, not a real DM bit */
! 166: #define DML_RNG 0000200 /* ring */
! 167: #define DML_CAR 0000100 /* carrier detect */
! 168: #define DML_CTS 0000040 /* clear to send */
! 169: #define DML_SR 0000020 /* secondary receive */
! 170: #define DML_ST 0000010 /* secondary transmit */
! 171: #define DML_RTS 0000004 /* request to send */
! 172: #define DML_DTR 0000002 /* data terminal ready */
! 173: #define DML_LE 0000001 /* line enable */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to sccreg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / alpha / tc