Annotation of sys/arch/alpha/pci/tsreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: tsreg.h,v 1.4 2006/01/04 10:32:10 martin Exp $ */
! 2: /* $NetBSD: tsreg.h,v 1.1 1999/06/29 06:46:47 ross Exp $ */
! 3:
! 4: /*-
! 5: * Copyright (c) 1999 by Ross Harvey. All rights reserved.
! 6: *
! 7: * Redistribution and use in source and binary forms, with or without
! 8: * modification, are permitted provided that the following conditions
! 9: * are met:
! 10: * 1. Redistributions of source code must retain the above copyright
! 11: * notice, this list of conditions and the following disclaimer.
! 12: * 2. Redistributions in binary form must reproduce the above copyright
! 13: * notice, this list of conditions and the following disclaimer in the
! 14: * documentation and/or other materials provided with the distribution.
! 15: * 3. All advertising materials mentioning features or use of this software
! 16: * must display the following acknowledgement:
! 17: * This product includes software developed by Ross Harvey.
! 18: * 4. The name of Ross Harvey may not be used to endorse or promote products
! 19: * derived from this software without specific prior written permission.
! 20: *
! 21: * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
! 22: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 23: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
! 24: * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
! 25: * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 26: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 27: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 28: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 29: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 30: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 31: * SUCH DAMAGE.
! 32: *
! 33: */
! 34:
! 35: /*
! 36: * 21272 Core Logic registers and constants.
! 37: */
! 38:
! 39: #define tsreg() { Generate ctags(1) key. }
! 40:
! 41: /*
! 42: * Superpage pointer from physical address.
! 43: */
! 44: #define S_PAGE(phys) ((void *)ALPHA_PHYS_TO_K0SEG(phys))
! 45:
! 46: /*
! 47: * {LD,ST}QP: LoaD and STore Quad Physical
! 48: */
! 49: #define LDQP(a) (*(volatile long *)ALPHA_PHYS_TO_K0SEG(a))
! 50: #define STQP(a) LDQP(a)
! 51:
! 52: /*
! 53: * Define extraction functions for bit fields via length and left,right bitno
! 54: */
! 55: #define TSFIELD(r,offs,len) (((r) >> (offs)) & (~0UL >> (64 - (len))))
! 56: #define TSFIELDBB(r,lb,rb) TSFIELD((r), (rb), (lb) - (rb) + 1)
! 57:
! 58: /*
! 59: * EV6 has a new superpage which can pass through 44 address bits. (Umm, a
! 60: * superduperpage?) But, the firmware doesn't turn it on, so we use the old
! 61: * one and let the HW sign extend va/pa<40> to get us the pa<43> that makes
! 62: * the needed I/O space access. This is just as well; it means we don't have
! 63: * to worry about which GENERIC code might get called on other CPU models.
! 64: *
! 65: * E.g., we want this: 0x0801##a000##0000
! 66: * We use this: 0x0101##a000##0000
! 67: * ...mix in the old SP: 0xffff##fc00##0000##0000
! 68: * ...after PA sign ext: 0xffff##ff00##a000##0000
! 69: * (PA<42:41> ignored)
! 70: */
! 71:
! 72: /*
! 73: * This hack allows us to map the I/O address space without using
! 74: * the KSEG sign extension hack.
! 75: */
! 76: #define TS_PHYSADDR(x) \
! 77: (((x) & ~0x0100##0000##0000) | 0x0800##0000##0000)
! 78:
! 79: /*
! 80: * Cchip CSR Map
! 81: */
! 82:
! 83: #define TS_C_CSC 0x101##a000##0000UL /* Cchip System Configuration */
! 84:
! 85: # define CSC_P1P (1L << 14)
! 86: # define CSC_BC(r) TSFIELD((r), 0, 2)
! 87: # define CSC_AW (1L << 8)
! 88:
! 89: #define TS_C_MTR 0x101##a000##0040UL
! 90:
! 91: #define TS_C_MISC 0x101##a000##0080UL /* Miscellaneous Register */
! 92:
! 93: # define MISC_REV(r) TSFIELD((r), 39, 8)
! 94:
! 95: #define TS_C_MPD 0x101##a000##00c0UL
! 96:
! 97: #define TS_C_AAR0 0x101##a000##0100UL
! 98: #define TS_C_AAR1 0x101##a000##0140UL
! 99: #define TS_C_AAR2 0x101##a000##0180UL
! 100: #define TS_C_AAR3 0x101##a000##01c0UL
! 101:
! 102: # define AAR_ASIZ(r) TSFIELD((r), 12, 4)
! 103: # define AAR_SPLIT (1L << 8)
! 104:
! 105: #define TS_C_DIM0 0x101##a000##0200UL
! 106: #define TS_C_DIM1 0x101##a000##0240UL
! 107: #define TS_C_DIR0 0x101##a000##0280UL
! 108: #define TS_C_DIR1 0x101##a000##02c0UL
! 109: #define TS_C_DRIR 0x101##a000##0300UL
! 110: #define TS_C_PRBEN 0x101##a000##0340UL
! 111: #define TS_C_IIC0 0x101##a000##0380UL
! 112: #define TS_C_IIC1 0x101##a000##03c0UL
! 113: #define TS_C_MPR0 0x101##a000##0400UL
! 114: #define TS_C_MPR1 0x101##a000##0440UL
! 115: #define TS_C_MPR2 0x101##a000##0480UL
! 116: #define TS_C_MPR3 0x101##a000##04c0UL
! 117: #define TS_C_MCTL 0x101##a000##0500UL
! 118:
! 119: #define TS_C_TTR 0x101##a000##0580UL
! 120: #define TS_C_TDR 0x101##a000##05c0UL
! 121:
! 122: /*
! 123: * Dchip CSR Map
! 124: */
! 125:
! 126: #define TS_D_DSC 0x101##b000##0800UL
! 127: #define TS_D_STR 0x101##b000##0840UL
! 128: #define TS_D_DREV 0x101##b000##0880UL
! 129: #define TS_D_DSC2 0x101##b000##08c0UL
! 130:
! 131: /*
! 132: * Pchip CSR Offsets
! 133: */
! 134:
! 135: #define P_WSBA0 0x0000
! 136: #define P_WSBA1 0x0040
! 137: #define P_WSBA2 0x0080
! 138: #define P_WSBA3 0x00c0
! 139:
! 140: # define WSBA_ADDR(r) (TSFIELDBB((r), 31, 20) << 20)
! 141: # define WSBA_SG 2
! 142: # define WSBA_ENA 1
! 143:
! 144: #define P_WSM0 0x0100
! 145: #define P_WSM1 0x0140
! 146: #define P_WSM2 0x0180
! 147: #define P_WSM3 0x01c0
! 148:
! 149: # define WSM_AM(r) TSFIELDBB((r), 31, 20)
! 150: # define WSM_LEN(r) ((WSM_AM(r) + 1) << 20)
! 151:
! 152: #define P_TBA0 0x0200
! 153: #define P_TBA1 0x0240
! 154: #define P_TBA2 0x0280
! 155: #define P_TBA3 0x02c0
! 156:
! 157: #define P_PCTL 0x0300
! 158: #define P_PLAT 0x0340
! 159: /* reserved 0x0380 */
! 160: #define P_PERROR 0x03c0
! 161:
! 162: #define P_PERRMASK 0x0400
! 163: #define P_PERRSET 0x0440
! 164: #define P_TLBIV 0x0480
! 165: #define P_TLBIA 0x04c0
! 166:
! 167: #define P_PMONCTL 0x0500
! 168: #define P_PMONCNT 0x0540
! 169:
! 170: #define P_SPRST 0x0800
! 171:
! 172: #define TS_STEP 0x40
! 173:
! 174: /*
! 175: * Pchip I/O offsets
! 176: */
! 177:
! 178: #define P_CSRBASE 0x001##8000##0000UL
! 179: #define P_PCI_MEM 0x800##0000##0000UL
! 180: #define P_PCI_IO 0x001##fc00##0000UL
! 181: #define P_PCI_CONFIG 0x001##fe00##0000UL
! 182:
! 183: /*
! 184: * Construct EV6 I/O Space Address for Pchip 0 and Pchip 1.
! 185: */
! 186:
! 187: #define TS_P0(offs) (0x100##0000##0000UL + (offs))
! 188: #define TS_P1(offs) (0x102##0000##0000UL + (offs))
! 189: #define TS_Pn(n, offs) (0x100##0000##0000UL + 0x2##0000##0000UL * (n) + (offs))
! 190:
! 191: /*
! 192: * Tsunami Generic Register Type
! 193: */
! 194: typedef struct _ts_gr {
! 195: volatile u_int64_t tsg_r;
! 196: long tsg_deadspace[7];
! 197: } TS_GR;
! 198:
! 199: /*
! 200: * Tsunami Pchip
! 201: */
! 202: struct ts_pchip {
! 203: TS_GR tsp_wsba[4]; /* Window Space Base Address */
! 204:
! 205: TS_GR tsp_wsm[4]; /* Window Space Mask */
! 206:
! 207: TS_GR tsp_tba[4]; /* Translated Base Address */
! 208:
! 209: TS_GR tsp_pctl; /* Pchip Control */
! 210: TS_GR tsp_plat; /* Pchip Latency */
! 211: TS_GR tsp_resA;
! 212: TS_GR tsp_error; /* Pchip Error */
! 213:
! 214: TS_GR tsp_perrmask; /* Pchip Error Mask */
! 215: TS_GR tsp_perrset; /* Pchip Error Set */
! 216: TS_GR tsp_tlbiv; /* Translation Buffer Invalidate Virtual */
! 217: TS_GR tsp_tlbia; /* Translation Buffer Invalidate All */
! 218:
! 219: TS_GR tsp_pmonctl; /* PChip Monitor Control */
! 220: TS_GR tsp_pmoncnt; /* PChip Monitor Counters */
! 221: TS_GR tsp_resB;
! 222: TS_GR tsp_resC;
! 223:
! 224: TS_GR tsp_resD_K[8];
! 225:
! 226: TS_GR tsp_sprts; /* ??? */
! 227: };
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