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1.1 nbrk 1: /* $OpenBSD: pci_swiz_bus_io_chipdep.c,v 1.4 2007/03/16 21:22:27 robert Exp $ */
2: /* $NetBSD: pcs_bus_io_common.c,v 1.14 1996/12/02 22:19:35 cgd Exp $ */
3:
4: /*
5: * Copyright (c) 1995, 1996 Carnegie-Mellon University.
6: * All rights reserved.
7: *
8: * Author: Chris G. Demetriou
9: *
10: * Permission to use, copy, modify and distribute this software and
11: * its documentation is hereby granted, provided that both the copyright
12: * notice and this permission notice appear in all copies of the
13: * software, derivative works or modified versions, and any portions
14: * thereof, and that both notices appear in supporting documentation.
15: *
16: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19: *
20: * Carnegie Mellon requests users of this software to return to
21: *
22: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23: * School of Computer Science
24: * Carnegie Mellon University
25: * Pittsburgh PA 15213-3890
26: *
27: * any improvements or extensions that they make and grant Carnegie the
28: * rights to redistribute these changes.
29: */
30:
31: /*
32: * Common PCI Chipset "bus I/O" functions, for chipsets which have to
33: * deal with only a single PCI interface chip in a machine.
34: *
35: * uses:
36: * CHIP name of the 'chip' it's being compiled for.
37: * CHIP_IO_BASE Sparse I/O space base to use.
38: */
39:
40: #include <sys/extent.h>
41:
42: #define __C(A,B) __CONCAT(A,B)
43: #define __S(S) __STRING(S)
44:
45: #ifndef CHIP_EXTENT_NAME
46: #define CHIP_EXTENT_NAME(v) __S(__C(CHIP,_bus_io))
47: #endif
48:
49: #ifndef CHIP_EXTENT_STORAGE
50: #define CHIP_EXTENT_STORAGE(v) __C(CHIP,_io_ex_storage)
51: static long
52: __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
53: #endif
54:
55: /* mapping/unmapping */
56: int __C(CHIP,_io_map)(void *, bus_addr_t, bus_size_t, int,
57: bus_space_handle_t *);
58: void __C(CHIP,_io_unmap)(void *, bus_space_handle_t,
59: bus_size_t);
60: int __C(CHIP,_io_subregion)(void *, bus_space_handle_t,
61: bus_size_t, bus_size_t, bus_space_handle_t *);
62:
63: /* allocation/deallocation */
64: int __C(CHIP,_io_alloc)(void *, bus_addr_t, bus_addr_t,
65: bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *,
66: bus_space_handle_t *);
67: void __C(CHIP,_io_free)(void *, bus_space_handle_t,
68: bus_size_t);
69:
70: /* barrier */
71: inline void __C(CHIP,_io_barrier)(void *, bus_space_handle_t,
72: bus_size_t, bus_size_t, int);
73:
74: /* read (single) */
75: inline u_int8_t __C(CHIP,_io_read_1)(void *, bus_space_handle_t,
76: bus_size_t);
77: inline u_int16_t __C(CHIP,_io_read_2)(void *, bus_space_handle_t,
78: bus_size_t);
79: inline u_int32_t __C(CHIP,_io_read_4)(void *, bus_space_handle_t,
80: bus_size_t);
81: inline u_int64_t __C(CHIP,_io_read_8)(void *, bus_space_handle_t,
82: bus_size_t);
83:
84: /* read multiple */
85: void __C(CHIP,_io_read_multi_1)(void *, bus_space_handle_t,
86: bus_size_t, u_int8_t *, bus_size_t);
87: void __C(CHIP,_io_read_multi_2)(void *, bus_space_handle_t,
88: bus_size_t, u_int16_t *, bus_size_t);
89: void __C(CHIP,_io_read_multi_4)(void *, bus_space_handle_t,
90: bus_size_t, u_int32_t *, bus_size_t);
91: void __C(CHIP,_io_read_multi_8)(void *, bus_space_handle_t,
92: bus_size_t, u_int64_t *, bus_size_t);
93:
94: /* read region */
95: void __C(CHIP,_io_read_region_1)(void *, bus_space_handle_t,
96: bus_size_t, u_int8_t *, bus_size_t);
97: void __C(CHIP,_io_read_region_2)(void *, bus_space_handle_t,
98: bus_size_t, u_int16_t *, bus_size_t);
99: void __C(CHIP,_io_read_region_4)(void *, bus_space_handle_t,
100: bus_size_t, u_int32_t *, bus_size_t);
101: void __C(CHIP,_io_read_region_8)(void *, bus_space_handle_t,
102: bus_size_t, u_int64_t *, bus_size_t);
103:
104: /* write (single) */
105: inline void __C(CHIP,_io_write_1)(void *, bus_space_handle_t,
106: bus_size_t, u_int8_t);
107: inline void __C(CHIP,_io_write_2)(void *, bus_space_handle_t,
108: bus_size_t, u_int16_t);
109: inline void __C(CHIP,_io_write_4)(void *, bus_space_handle_t,
110: bus_size_t, u_int32_t);
111: inline void __C(CHIP,_io_write_8)(void *, bus_space_handle_t,
112: bus_size_t, u_int64_t);
113:
114: /* write multiple */
115: void __C(CHIP,_io_write_multi_1)(void *, bus_space_handle_t,
116: bus_size_t, const u_int8_t *, bus_size_t);
117: void __C(CHIP,_io_write_multi_2)(void *, bus_space_handle_t,
118: bus_size_t, const u_int16_t *, bus_size_t);
119: void __C(CHIP,_io_write_multi_4)(void *, bus_space_handle_t,
120: bus_size_t, const u_int32_t *, bus_size_t);
121: void __C(CHIP,_io_write_multi_8)(void *, bus_space_handle_t,
122: bus_size_t, const u_int64_t *, bus_size_t);
123:
124: /* write region */
125: void __C(CHIP,_io_write_region_1)(void *, bus_space_handle_t,
126: bus_size_t, const u_int8_t *, bus_size_t);
127: void __C(CHIP,_io_write_region_2)(void *, bus_space_handle_t,
128: bus_size_t, const u_int16_t *, bus_size_t);
129: void __C(CHIP,_io_write_region_4)(void *, bus_space_handle_t,
130: bus_size_t, const u_int32_t *, bus_size_t);
131: void __C(CHIP,_io_write_region_8)(void *, bus_space_handle_t,
132: bus_size_t, const u_int64_t *, bus_size_t);
133:
134: /* set multiple */
135: void __C(CHIP,_io_set_multi_1)(void *, bus_space_handle_t,
136: bus_size_t, u_int8_t, bus_size_t);
137: void __C(CHIP,_io_set_multi_2)(void *, bus_space_handle_t,
138: bus_size_t, u_int16_t, bus_size_t);
139: void __C(CHIP,_io_set_multi_4)(void *, bus_space_handle_t,
140: bus_size_t, u_int32_t, bus_size_t);
141: void __C(CHIP,_io_set_multi_8)(void *, bus_space_handle_t,
142: bus_size_t, u_int64_t, bus_size_t);
143:
144: /* set region */
145: void __C(CHIP,_io_set_region_1)(void *, bus_space_handle_t,
146: bus_size_t, u_int8_t, bus_size_t);
147: void __C(CHIP,_io_set_region_2)(void *, bus_space_handle_t,
148: bus_size_t, u_int16_t, bus_size_t);
149: void __C(CHIP,_io_set_region_4)(void *, bus_space_handle_t,
150: bus_size_t, u_int32_t, bus_size_t);
151: void __C(CHIP,_io_set_region_8)(void *, bus_space_handle_t,
152: bus_size_t, u_int64_t, bus_size_t);
153:
154: /* copy */
155: void __C(CHIP,_io_copy_1)(void *, bus_space_handle_t,
156: bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
157: void __C(CHIP,_io_copy_2)(void *, bus_space_handle_t,
158: bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
159: void __C(CHIP,_io_copy_4)(void *, bus_space_handle_t,
160: bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
161: void __C(CHIP,_io_copy_8)(void *, bus_space_handle_t,
162: bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
163:
164: /* read multiple raw */
165: void __C(CHIP,_io_read_raw_multi_2)(void *, bus_space_handle_t,
166: bus_size_t, u_int8_t *, bus_size_t);
167: void __C(CHIP,_io_read_raw_multi_4)(void *, bus_space_handle_t,
168: bus_size_t, u_int8_t *, bus_size_t);
169: void __C(CHIP,_io_read_raw_multi_8)(void *, bus_space_handle_t,
170: bus_size_t, u_int8_t *, bus_size_t);
171:
172: /* write multiple raw */
173: void __C(CHIP,_io_write_raw_multi_2)(void *,
174: bus_space_handle_t, bus_size_t, const u_int8_t *,
175: bus_size_t);
176: void __C(CHIP,_io_write_raw_multi_4)(void *,
177: bus_space_handle_t, bus_size_t, const u_int8_t *,
178: bus_size_t);
179: void __C(CHIP,_io_write_raw_multi_8)(void *,
180: bus_space_handle_t, bus_size_t, const u_int8_t *,
181: bus_size_t);
182:
183: void
184: __C(CHIP,_bus_io_init)(t, v)
185: bus_space_tag_t t;
186: void *v;
187: {
188: struct extent *ex;
189:
190: /*
191: * Initialize the bus space tag.
192: */
193:
194: /* cookie */
195: t->abs_cookie = v;
196:
197: /* mapping/unmapping */
198: t->abs_map = __C(CHIP,_io_map);
199: t->abs_unmap = __C(CHIP,_io_unmap);
200: t->abs_subregion = __C(CHIP,_io_subregion);
201:
202: /* allocation/deallocation */
203: t->abs_alloc = __C(CHIP,_io_alloc);
204: t->abs_free = __C(CHIP,_io_free);
205:
206: /* barrier */
207: t->abs_barrier = __C(CHIP,_io_barrier);
208:
209: /* read (single) */
210: t->abs_r_1 = __C(CHIP,_io_read_1);
211: t->abs_r_2 = __C(CHIP,_io_read_2);
212: t->abs_r_4 = __C(CHIP,_io_read_4);
213: t->abs_r_8 = __C(CHIP,_io_read_8);
214:
215: /* read multiple */
216: t->abs_rm_1 = __C(CHIP,_io_read_multi_1);
217: t->abs_rm_2 = __C(CHIP,_io_read_multi_2);
218: t->abs_rm_4 = __C(CHIP,_io_read_multi_4);
219: t->abs_rm_8 = __C(CHIP,_io_read_multi_8);
220:
221: /* read region */
222: t->abs_rr_1 = __C(CHIP,_io_read_region_1);
223: t->abs_rr_2 = __C(CHIP,_io_read_region_2);
224: t->abs_rr_4 = __C(CHIP,_io_read_region_4);
225: t->abs_rr_8 = __C(CHIP,_io_read_region_8);
226:
227: /* write (single) */
228: t->abs_w_1 = __C(CHIP,_io_write_1);
229: t->abs_w_2 = __C(CHIP,_io_write_2);
230: t->abs_w_4 = __C(CHIP,_io_write_4);
231: t->abs_w_8 = __C(CHIP,_io_write_8);
232:
233: /* write multiple */
234: t->abs_wm_1 = __C(CHIP,_io_write_multi_1);
235: t->abs_wm_2 = __C(CHIP,_io_write_multi_2);
236: t->abs_wm_4 = __C(CHIP,_io_write_multi_4);
237: t->abs_wm_8 = __C(CHIP,_io_write_multi_8);
238:
239: /* write region */
240: t->abs_wr_1 = __C(CHIP,_io_write_region_1);
241: t->abs_wr_2 = __C(CHIP,_io_write_region_2);
242: t->abs_wr_4 = __C(CHIP,_io_write_region_4);
243: t->abs_wr_8 = __C(CHIP,_io_write_region_8);
244:
245: /* set multiple */
246: t->abs_sm_1 = __C(CHIP,_io_set_multi_1);
247: t->abs_sm_2 = __C(CHIP,_io_set_multi_2);
248: t->abs_sm_4 = __C(CHIP,_io_set_multi_4);
249: t->abs_sm_8 = __C(CHIP,_io_set_multi_8);
250:
251: /* set region */
252: t->abs_sr_1 = __C(CHIP,_io_set_region_1);
253: t->abs_sr_2 = __C(CHIP,_io_set_region_2);
254: t->abs_sr_4 = __C(CHIP,_io_set_region_4);
255: t->abs_sr_8 = __C(CHIP,_io_set_region_8);
256:
257: /* copy */
258: t->abs_c_1 = __C(CHIP,_io_copy_1);
259: t->abs_c_2 = __C(CHIP,_io_copy_2);
260: t->abs_c_4 = __C(CHIP,_io_copy_4);
261: t->abs_c_8 = __C(CHIP,_io_copy_8);
262:
263: /* read multiple raw */
264: t->abs_rrm_2 = __C(CHIP,_io_read_raw_multi_2);
265: t->abs_rrm_4 = __C(CHIP,_io_read_raw_multi_4);
266: t->abs_rrm_8 = __C(CHIP,_io_read_raw_multi_8);
267:
268: /* write multiple raw*/
269: t->abs_wrm_2 = __C(CHIP,_io_write_raw_multi_2);
270: t->abs_wrm_4 = __C(CHIP,_io_write_raw_multi_4) ;
271: t->abs_wrm_8 = __C(CHIP,_io_write_raw_multi_8);
272:
273:
274: /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */
275: ex = extent_create(CHIP_EXTENT_NAME(v), 0x0UL, 0xffffffffUL,
276: M_DEVBUF, (caddr_t)CHIP_EXTENT_STORAGE(v),
277: sizeof(CHIP_EXTENT_STORAGE(v)), EX_NOWAIT);
278: extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT);
279:
280: #ifdef CHIP_IO_W1_BUS_START
281: #ifdef EXTENT_DEBUG
282: printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v),
283: CHIP_IO_W1_BUS_END(v));
284: #endif
285: extent_free(ex, CHIP_IO_W1_BUS_START(v),
286: CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT);
287: #endif
288: #ifdef CHIP_IO_W2_BUS_START
289: #ifdef EXTENT_DEBUG
290: printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v),
291: CHIP_IO_W2_BUS_END(v));
292: #endif
293: extent_free(ex, CHIP_IO_W2_BUS_START(v),
294: CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT);
295: #endif
296:
297: #ifdef EXTENT_DEBUG
298: extent_print(ex);
299: #endif
300: CHIP_IO_EXTENT(v) = ex;
301: }
302:
303: int
304: __C(CHIP,_io_map)(v, ioaddr, iosize, cacheable, iohp)
305: void *v;
306: bus_addr_t ioaddr;
307: bus_size_t iosize;
308: int cacheable;
309: bus_space_handle_t *iohp;
310: {
311: int error;
312:
313: #ifdef EXTENT_DEBUG
314: printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1);
315: #endif
316: error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize,
317: EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0));
318: if (error) {
319: #ifdef EXTENT_DEBUG
320: printf("io: allocation failed (%d)\n", error);
321: extent_print(CHIP_IO_EXTENT(v));
322: #endif
323: return (error);
324: }
325:
326: #ifdef CHIP_IO_W1_BUS_START
327: if (ioaddr >= CHIP_IO_W1_BUS_START(v) &&
328: ioaddr <= CHIP_IO_W1_BUS_END(v)) {
329: *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_SYS_START(v)) >> 5) +
330: (ioaddr - CHIP_IO_W1_BUS_START(v));
331: } else
332: #endif
333: #ifdef CHIP_IO_W2_BUS_START
334: if (ioaddr >= CHIP_IO_W2_BUS_START(v) &&
335: ioaddr <= CHIP_IO_W2_BUS_END(v)) {
336: *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_SYS_START(v)) >> 5) +
337: (ioaddr - CHIP_IO_W2_BUS_START(v));
338: } else
339: #endif
340: {
341: printf("\n");
342: #ifdef CHIP_IO_W1_BUS_START
343: printf("%s: window[1]=0x%lx-0x%lx\n",
344: __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v),
345: CHIP_IO_W1_BUS_END(v));
346: #endif
347: #ifdef CHIP_IO_W2_BUS_START
348: printf("%s: window[2]=0x%lx-0x%lx\n",
349: __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v),
350: CHIP_IO_W2_BUS_END(v));
351: #endif
352: panic("%s: don't know how to map %lx",
353: __S(__C(CHIP,_io_map)), ioaddr);
354: }
355:
356: return (0);
357: }
358:
359: void
360: __C(CHIP,_io_unmap)(v, ioh, iosize)
361: void *v;
362: bus_space_handle_t ioh;
363: bus_size_t iosize;
364: {
365: bus_addr_t ioaddr;
366: int error;
367:
368: #ifdef EXTENT_DEBUG
369: printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize);
370: #endif
371:
372: ioh = ALPHA_K0SEG_TO_PHYS(ioh << 5) >> 5;
373:
374: #ifdef CHIP_IO_W1_BUS_START
375: if ((ioh << 5) >= CHIP_IO_W1_SYS_START(v) &&
376: (ioh << 5) <= CHIP_IO_W1_SYS_END(v)) {
377: ioaddr = CHIP_IO_W1_BUS_START(v) +
378: (ioh - (CHIP_IO_W1_SYS_START(v) >> 5));
379: } else
380: #endif
381: #ifdef CHIP_IO_W2_BUS_START
382: if ((ioh << 5) >= CHIP_IO_W2_SYS_START(v) &&
383: (ioh << 5) <= CHIP_IO_W2_SYS_END(v)) {
384: ioaddr = CHIP_IO_W2_BUS_START(v) +
385: (ioh - (CHIP_IO_W2_SYS_START(v) >> 5));
386: } else
387: #endif
388: {
389: printf("\n");
390: #ifdef CHIP_IO_W1_BUS_START
391: printf("%s: sys window[1]=0x%lx-0x%lx\n",
392: __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v),
393: CHIP_IO_W1_SYS_END(v));
394: #endif
395: #ifdef CHIP_IO_W2_BUS_START
396: printf("%s: sys window[2]=0x%lx-0x%lx\n",
397: __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v),
398: CHIP_IO_W2_SYS_END(v));
399: #endif
400: panic("%s: don't know how to unmap %lx",
401: __S(__C(CHIP,_io_unmap)), (ioh << 5));
402: }
403:
404: #ifdef EXTENT_DEBUG
405: printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1);
406: #endif
407: error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize,
408: EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0));
409: if (error) {
410: printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n",
411: __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1,
412: error);
413: #ifdef EXTENT_DEBUG
414: extent_print(CHIP_IO_EXTENT(v));
415: #endif
416: }
417: }
418:
419: int
420: __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh)
421: void *v;
422: bus_space_handle_t ioh, *nioh;
423: bus_size_t offset, size;
424: {
425:
426: *nioh = ioh + offset;
427: return (0);
428: }
429:
430: int
431: __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, cacheable,
432: addrp, bshp)
433: void *v;
434: bus_addr_t rstart, rend, *addrp;
435: bus_size_t size, align, boundary;
436: int cacheable;
437: bus_space_handle_t *bshp;
438: {
439:
440: /* XXX XXX XXX XXX XXX XXX */
441: panic("%s not implemented", __S(__C(CHIP,_io_alloc)));
442: }
443:
444: void
445: __C(CHIP,_io_free)(v, bsh, size)
446: void *v;
447: bus_space_handle_t bsh;
448: bus_size_t size;
449: {
450:
451: /* XXX XXX XXX XXX XXX XXX */
452: panic("%s not implemented", __S(__C(CHIP,_io_free)));
453: }
454:
455: inline void
456: __C(CHIP,_io_barrier)(v, h, o, l, f)
457: void *v;
458: bus_space_handle_t h;
459: bus_size_t o, l;
460: int f;
461: {
462:
463: if ((f & BUS_BARRIER_READ) != 0)
464: alpha_mb();
465: else if ((f & BUS_BARRIER_WRITE) != 0)
466: alpha_wmb();
467: }
468:
469: inline u_int8_t
470: __C(CHIP,_io_read_1)(v, ioh, off)
471: void *v;
472: bus_space_handle_t ioh;
473: bus_size_t off;
474: {
475: register bus_space_handle_t tmpioh;
476: register u_int32_t *port, val;
477: register u_int8_t rval;
478: register int offset;
479:
480: alpha_mb();
481:
482: tmpioh = ioh + off;
483: offset = tmpioh & 3;
484: port = (u_int32_t *)((tmpioh << 5) | (0 << 3));
485: val = *port;
486: rval = ((val) >> (8 * offset)) & 0xff;
487:
488: return rval;
489: }
490:
491: inline u_int16_t
492: __C(CHIP,_io_read_2)(v, ioh, off)
493: void *v;
494: bus_space_handle_t ioh;
495: bus_size_t off;
496: {
497: register bus_space_handle_t tmpioh;
498: register u_int32_t *port, val;
499: register u_int16_t rval;
500: register int offset;
501:
502: alpha_mb();
503:
504: tmpioh = ioh + off;
505: offset = tmpioh & 3;
506: port = (u_int32_t *)((tmpioh << 5) | (1 << 3));
507: val = *port;
508: rval = ((val) >> (8 * offset)) & 0xffff;
509:
510: return rval;
511: }
512:
513: inline u_int32_t
514: __C(CHIP,_io_read_4)(v, ioh, off)
515: void *v;
516: bus_space_handle_t ioh;
517: bus_size_t off;
518: {
519: register bus_space_handle_t tmpioh;
520: register u_int32_t *port, val;
521: register u_int32_t rval;
522: register int offset;
523:
524: alpha_mb();
525:
526: tmpioh = ioh + off;
527: offset = tmpioh & 3;
528: port = (u_int32_t *)((tmpioh << 5) | (3 << 3));
529: val = *port;
530: #if 0
531: rval = ((val) >> (8 * offset)) & 0xffffffff;
532: #else
533: rval = val;
534: #endif
535:
536: return rval;
537: }
538:
539: inline u_int64_t
540: __C(CHIP,_io_read_8)(v, ioh, off)
541: void *v;
542: bus_space_handle_t ioh;
543: bus_size_t off;
544: {
545:
546: /* XXX XXX XXX */
547: panic("%s not implemented", __S(__C(CHIP,_io_read_8)));
548: }
549:
550: #define CHIP_io_read_multi_N(BYTES,TYPE) \
551: void \
552: __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \
553: void *v; \
554: bus_space_handle_t h; \
555: bus_size_t o, c; \
556: TYPE *a; \
557: { \
558: \
559: while (c-- > 0) { \
560: __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \
561: BUS_BARRIER_READ); \
562: *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \
563: } \
564: }
565: CHIP_io_read_multi_N(1,u_int8_t)
566: CHIP_io_read_multi_N(2,u_int16_t)
567: CHIP_io_read_multi_N(4,u_int32_t)
568: CHIP_io_read_multi_N(8,u_int64_t)
569:
570: #define CHIP_io_read_region_N(BYTES,TYPE) \
571: void \
572: __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \
573: void *v; \
574: bus_space_handle_t h; \
575: bus_size_t o, c; \
576: TYPE *a; \
577: { \
578: \
579: while (c-- > 0) { \
580: *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \
581: o += sizeof *a; \
582: } \
583: }
584: CHIP_io_read_region_N(1,u_int8_t)
585: CHIP_io_read_region_N(2,u_int16_t)
586: CHIP_io_read_region_N(4,u_int32_t)
587: CHIP_io_read_region_N(8,u_int64_t)
588:
589: inline void
590: __C(CHIP,_io_write_1)(v, ioh, off, val)
591: void *v;
592: bus_space_handle_t ioh;
593: bus_size_t off;
594: u_int8_t val;
595: {
596: register bus_space_handle_t tmpioh;
597: register u_int32_t *port, nval;
598: register int offset;
599:
600: tmpioh = ioh + off;
601: offset = tmpioh & 3;
602: nval = val << (8 * offset);
603: port = (u_int32_t *)((tmpioh << 5) | (0 << 3));
604: *port = nval;
605: alpha_mb();
606: }
607:
608: inline void
609: __C(CHIP,_io_write_2)(v, ioh, off, val)
610: void *v;
611: bus_space_handle_t ioh;
612: bus_size_t off;
613: u_int16_t val;
614: {
615: register bus_space_handle_t tmpioh;
616: register u_int32_t *port, nval;
617: register int offset;
618:
619: tmpioh = ioh + off;
620: offset = tmpioh & 3;
621: nval = val << (8 * offset);
622: port = (u_int32_t *)((tmpioh << 5) | (1 << 3));
623: *port = nval;
624: alpha_mb();
625: }
626:
627: inline void
628: __C(CHIP,_io_write_4)(v, ioh, off, val)
629: void *v;
630: bus_space_handle_t ioh;
631: bus_size_t off;
632: u_int32_t val;
633: {
634: register bus_space_handle_t tmpioh;
635: register u_int32_t *port, nval;
636: register int offset;
637:
638: tmpioh = ioh + off;
639: offset = tmpioh & 3;
640: nval = val /*<< (8 * offset)*/;
641: port = (u_int32_t *)((tmpioh << 5) | (3 << 3));
642: *port = nval;
643: alpha_mb();
644: }
645:
646: inline void
647: __C(CHIP,_io_write_8)(v, ioh, off, val)
648: void *v;
649: bus_space_handle_t ioh;
650: bus_size_t off;
651: u_int64_t val;
652: {
653:
654: /* XXX XXX XXX */
655: panic("%s not implemented", __S(__C(CHIP,_io_write_8)));
656: alpha_mb();
657: }
658:
659: #define CHIP_io_write_multi_N(BYTES,TYPE) \
660: void \
661: __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \
662: void *v; \
663: bus_space_handle_t h; \
664: bus_size_t o, c; \
665: const TYPE *a; \
666: { \
667: \
668: while (c-- > 0) { \
669: __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \
670: __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \
671: BUS_BARRIER_WRITE); \
672: } \
673: }
674: CHIP_io_write_multi_N(1,u_int8_t)
675: CHIP_io_write_multi_N(2,u_int16_t)
676: CHIP_io_write_multi_N(4,u_int32_t)
677: CHIP_io_write_multi_N(8,u_int64_t)
678:
679: #define CHIP_io_write_region_N(BYTES,TYPE) \
680: void \
681: __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \
682: void *v; \
683: bus_space_handle_t h; \
684: bus_size_t o, c; \
685: const TYPE *a; \
686: { \
687: \
688: while (c-- > 0) { \
689: __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \
690: o += sizeof *a; \
691: } \
692: }
693: CHIP_io_write_region_N(1,u_int8_t)
694: CHIP_io_write_region_N(2,u_int16_t)
695: CHIP_io_write_region_N(4,u_int32_t)
696: CHIP_io_write_region_N(8,u_int64_t)
697:
698: #define CHIP_io_set_multi_N(BYTES,TYPE) \
699: void \
700: __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \
701: void *v; \
702: bus_space_handle_t h; \
703: bus_size_t o, c; \
704: TYPE val; \
705: { \
706: \
707: while (c-- > 0) { \
708: __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \
709: __C(CHIP,_io_barrier)(v, h, o, sizeof val, \
710: BUS_BARRIER_WRITE); \
711: } \
712: }
713: CHIP_io_set_multi_N(1,u_int8_t)
714: CHIP_io_set_multi_N(2,u_int16_t)
715: CHIP_io_set_multi_N(4,u_int32_t)
716: CHIP_io_set_multi_N(8,u_int64_t)
717:
718: #define CHIP_io_set_region_N(BYTES,TYPE) \
719: void \
720: __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \
721: void *v; \
722: bus_space_handle_t h; \
723: bus_size_t o, c; \
724: TYPE val; \
725: { \
726: \
727: while (c-- > 0) { \
728: __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \
729: o += sizeof val; \
730: } \
731: }
732: CHIP_io_set_region_N(1,u_int8_t)
733: CHIP_io_set_region_N(2,u_int16_t)
734: CHIP_io_set_region_N(4,u_int32_t)
735: CHIP_io_set_region_N(8,u_int64_t)
736:
737: #define CHIP_io_copy_N(BYTES) \
738: void \
739: __C(__C(CHIP,_io_copy_),BYTES)(v, h1, o1, h2, o2, c) \
740: void *v; \
741: bus_space_handle_t h1, h2; \
742: bus_size_t o1, o2, c; \
743: { \
744: bus_size_t i, o; \
745: \
746: for (i = 0, o = 0; i < c; i++, o += BYTES) \
747: __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \
748: __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \
749: }
750: CHIP_io_copy_N(1)
751: CHIP_io_copy_N(2)
752: CHIP_io_copy_N(4)
753: CHIP_io_copy_N(8)
754:
755: #define CHIP_io_read_raw_multi_N(BYTES,TYPE) \
756: void \
757: __C(__C(CHIP,_io_read_raw_multi_),BYTES)(v, h, o, a, c) \
758: void *v; \
759: bus_space_handle_t h; \
760: bus_size_t o, c; \
761: u_int8_t *a; \
762: { \
763: TYPE temp; \
764: int i; \
765: \
766: while (c > 0) { \
767: __C(CHIP,_io_barrier)(v, h, o, BYTES, BUS_BARRIER_READ); \
768: temp = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \
769: i = MIN(c, BYTES); \
770: c -= i; \
771: while (i--) { \
772: *a++ = temp & 0xff; \
773: temp >>= 8; \
774: } \
775: } \
776: }
777: CHIP_io_read_raw_multi_N(2,u_int16_t)
778: CHIP_io_read_raw_multi_N(4,u_int32_t)
779: CHIP_io_read_raw_multi_N(8,u_int64_t)
780:
781: #define CHIP_io_write_raw_multi_N(BYTES,TYPE) \
782: void \
783: __C(__C(CHIP,_io_write_raw_multi_),BYTES)(v, h, o, a, c) \
784: void *v; \
785: bus_space_handle_t h; \
786: bus_size_t o, c; \
787: const u_int8_t *a; \
788: { \
789: TYPE temp; \
790: int i; \
791: \
792: while (c > 0) { \
793: temp = 0; \
794: for (i = BYTES - 1; i >= 0; i--) { \
795: temp <<= 8; \
796: if (i < c) \
797: temp |= *(a + i); \
798: } \
799: __C(__C(CHIP,_io_write_),BYTES)(v, h, o, temp); \
800: __C(CHIP,_io_barrier)(v, h, o, BYTES, BUS_BARRIER_WRITE); \
801: i = MIN(c, BYTES); \
802: c -= i; \
803: a += i; \
804: } \
805: }
806: CHIP_io_write_raw_multi_N(2,u_int16_t)
807: CHIP_io_write_raw_multi_N(4,u_int32_t)
808: CHIP_io_write_raw_multi_N(8,u_int64_t)