Annotation of sys/arch/alpha/pci/pci_eb64plus.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: pci_eb64plus.c,v 1.9 2006/06/15 20:08:29 brad Exp $ */
2: /* $NetBSD: pci_eb64plus.c,v 1.10 2001/07/27 00:25:20 thorpej Exp $ */
3:
4: /*-
5: * Copyright (c) 1998 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10: * NASA Ames Research Center.
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: * 3. All advertising materials mentioning features or use of this software
21: * must display the following acknowledgement:
22: * This product includes software developed by the NetBSD
23: * Foundation, Inc. and its contributors.
24: * 4. Neither the name of The NetBSD Foundation nor the names of its
25: * contributors may be used to endorse or promote products derived
26: * from this software without specific prior written permission.
27: *
28: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38: * POSSIBILITY OF SUCH DAMAGE.
39: */
40:
41: /*
42: * Copyright (c) 1995, 1996 Carnegie-Mellon University.
43: * All rights reserved.
44: *
45: * Author: Chris G. Demetriou
46: *
47: * Permission to use, copy, modify and distribute this software and
48: * its documentation is hereby granted, provided that both the copyright
49: * notice and this permission notice appear in all copies of the
50: * software, derivative works or modified versions, and any portions
51: * thereof, and that both notices appear in supporting documentation.
52: *
53: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
54: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
55: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
56: *
57: * Carnegie Mellon requests users of this software to return to
58: *
59: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
60: * School of Computer Science
61: * Carnegie Mellon University
62: * Pittsburgh PA 15213-3890
63: *
64: * any improvements or extensions that they make and grant Carnegie the
65: * rights to redistribute these changes.
66: */
67:
68: #include <sys/types.h>
69: #include <sys/param.h>
70: #include <sys/time.h>
71: #include <sys/systm.h>
72: #include <sys/errno.h>
73: #include <sys/malloc.h>
74: #include <sys/device.h>
75: #include <sys/syslog.h>
76:
77: #include <uvm/uvm_extern.h>
78:
79: #include <machine/autoconf.h>
80:
81: #include <dev/pci/pcireg.h>
82: #include <dev/pci/pcivar.h>
83:
84: #include <alpha/pci/apecsreg.h>
85: #include <alpha/pci/apecsvar.h>
86:
87: #include <alpha/pci/pci_eb64plus.h>
88:
89: #include "sio.h"
90: #if NSIO
91: #include <alpha/pci/siovar.h>
92: #endif
93:
94: int dec_eb64plus_intr_map(void *, pcitag_t, int, int,
95: pci_intr_handle_t *);
96: const char *dec_eb64plus_intr_string(void *, pci_intr_handle_t);
97: void *dec_eb64plus_intr_establish(void *, pci_intr_handle_t,
98: int, int (*func)(void *), void *, char *);
99: void dec_eb64plus_intr_disestablish(void *, void *);
100:
101: #define EB64PLUS_MAX_IRQ 32
102: #define PCI_STRAY_MAX 5
103:
104: struct alpha_shared_intr *eb64plus_pci_intr;
105:
106: bus_space_tag_t eb64plus_intrgate_iot;
107: bus_space_handle_t eb64plus_intrgate_ioh;
108:
109: void eb64plus_iointr(void *arg, unsigned long vec);
110: extern void eb64plus_intr_enable(int irq); /* pci_eb64plus_intr.S */
111: extern void eb64plus_intr_disable(int irq); /* pci_eb64plus_intr.S */
112:
113: void
114: pci_eb64plus_pickintr(acp)
115: struct apecs_config *acp;
116: {
117: bus_space_tag_t iot = &acp->ac_iot;
118: pci_chipset_tag_t pc = &acp->ac_pc;
119: int i;
120:
121: pc->pc_intr_v = acp;
122: pc->pc_intr_map = dec_eb64plus_intr_map;
123: pc->pc_intr_string = dec_eb64plus_intr_string;
124: pc->pc_intr_establish = dec_eb64plus_intr_establish;
125: pc->pc_intr_disestablish = dec_eb64plus_intr_disestablish;
126:
127: /* Not supported on the EB64+. */
128: pc->pc_pciide_compat_intr_establish = NULL;
129:
130: eb64plus_intrgate_iot = iot;
131: if (bus_space_map(eb64plus_intrgate_iot, 0x804, 3, 0,
132: &eb64plus_intrgate_ioh) != 0)
133: panic("pci_eb64plus_pickintr: couldn't map interrupt PLD");
134: for (i = 0; i < EB64PLUS_MAX_IRQ; i++)
135: eb64plus_intr_disable(i);
136:
137: eb64plus_pci_intr = alpha_shared_intr_alloc(EB64PLUS_MAX_IRQ);
138: for (i = 0; i < EB64PLUS_MAX_IRQ; i++) {
139: alpha_shared_intr_set_maxstrays(eb64plus_pci_intr, i,
140: PCI_STRAY_MAX);
141: }
142:
143: #if NSIO
144: sio_intr_setup(pc, iot);
145: #endif
146: }
147:
148: int
149: dec_eb64plus_intr_map(acv, bustag, buspin, line, ihp)
150: void *acv;
151: pcitag_t bustag;
152: int buspin, line;
153: pci_intr_handle_t *ihp;
154: {
155: struct apecs_config *acp = acv;
156: pci_chipset_tag_t pc = &acp->ac_pc;
157: int bus, device, function;
158:
159: if (buspin == 0) {
160: /* No IRQ used. */
161: return 1;
162: }
163: if (buspin > 4) {
164: printf("dec_eb64plus_intr_map: bad interrupt pin %d\n", buspin);
165: return 1;
166: }
167:
168: pci_decompose_tag(pc, bustag, &bus, &device, &function);
169:
170: /*
171: * The console places the interrupt mapping in the "line" value.
172: * A value of (char)-1 indicates there is no mapping.
173: */
174: if (line == 0xff) {
175: printf("dec_eb64plus_intr_map: no mapping for %d/%d/%d\n",
176: bus, device, function);
177: return (1);
178: }
179:
180: if (line >= EB64PLUS_MAX_IRQ)
181: panic("dec_eb64plus_intr_map: eb64+ irq too large (%d)",
182: line);
183:
184: *ihp = line;
185: return (0);
186: }
187:
188: const char *
189: dec_eb64plus_intr_string(acv, ih)
190: void *acv;
191: pci_intr_handle_t ih;
192: {
193: static char irqstr[15]; /* 11 + 2 + NULL + sanity */
194:
195: if (ih > EB64PLUS_MAX_IRQ)
196: panic("dec_eb64plus_intr_string: bogus eb64+ IRQ 0x%lx", ih);
197: snprintf(irqstr, sizeof irqstr, "eb64+ irq %ld", ih);
198: return (irqstr);
199: }
200:
201: void *
202: dec_eb64plus_intr_establish(acv, ih, level, func, arg, name)
203: void *acv;
204: pci_intr_handle_t ih;
205: int level;
206: int (*func)(void *);
207: void *arg;
208: char *name;
209: {
210: void *cookie;
211:
212: if (ih > EB64PLUS_MAX_IRQ)
213: panic("dec_eb64plus_intr_establish: bogus eb64+ IRQ 0x%lx",
214: ih);
215:
216: cookie = alpha_shared_intr_establish(eb64plus_pci_intr, ih, IST_LEVEL,
217: level, func, arg, name);
218:
219: if (cookie != NULL &&
220: alpha_shared_intr_firstactive(eb64plus_pci_intr, ih)) {
221: scb_set(0x900 + SCB_IDXTOVEC(ih), eb64plus_iointr, NULL);
222: eb64plus_intr_enable(ih);
223: }
224: return (cookie);
225: }
226:
227: void
228: dec_eb64plus_intr_disestablish(acv, cookie)
229: void *acv, *cookie;
230: {
231: struct alpha_shared_intrhand *ih = cookie;
232: unsigned int irq = ih->ih_num;
233: int s;
234:
235: s = splhigh();
236:
237: alpha_shared_intr_disestablish(eb64plus_pci_intr, cookie,
238: "eb64+ irq");
239: if (alpha_shared_intr_isactive(eb64plus_pci_intr, irq) == 0) {
240: eb64plus_intr_disable(irq);
241: alpha_shared_intr_set_dfltsharetype(eb64plus_pci_intr, irq,
242: IST_NONE);
243: scb_free(0x900 + SCB_IDXTOVEC(irq));
244: }
245:
246: splx(s);
247: }
248:
249: void
250: eb64plus_iointr(arg, vec)
251: void *arg;
252: unsigned long vec;
253: {
254: int irq;
255:
256: irq = SCB_VECTOIDX(vec - 0x900);
257:
258: if (!alpha_shared_intr_dispatch(eb64plus_pci_intr, irq)) {
259: alpha_shared_intr_stray(eb64plus_pci_intr, irq,
260: "eb64+ irq");
261: if (ALPHA_SHARED_INTR_DISABLE(eb64plus_pci_intr, irq))
262: eb64plus_intr_disable(irq);
263: } else
264: alpha_shared_intr_reset_strays(eb64plus_pci_intr, irq);
265: }
266:
267: #if 0 /* THIS DOES NOT WORK! see pci_eb64plus_intr.S. */
268: u_int8_t eb64plus_intr_mask[3] = { 0xff, 0xff, 0xff };
269:
270: void
271: eb64plus_intr_enable(irq)
272: int irq;
273: {
274: int byte = (irq / 8), bit = (irq % 8);
275:
276: #if 1
277: printf("eb64plus_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit);
278: #endif
279: eb64plus_intr_mask[byte] &= ~(1 << bit);
280:
281: bus_space_write_1(eb64plus_intrgate_iot, eb64plus_intrgate_ioh, byte,
282: eb64plus_intr_mask[byte]);
283: }
284:
285: void
286: eb64plus_intr_disable(irq)
287: int irq;
288: {
289: int byte = (irq / 8), bit = (irq % 8);
290:
291: #if 1
292: printf("eb64plus_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit);
293: #endif
294: eb64plus_intr_mask[byte] |= (1 << bit);
295:
296: bus_space_write_1(eb64plus_intrgate_iot, eb64plus_intrgate_ioh, byte,
297: eb64plus_intr_mask[byte]);
298: }
299: #endif
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