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1.1 nbrk 1: /* $OpenBSD: pci_bwx_bus_io_chipdep.c,v 1.5 2003/09/02 17:25:21 miod Exp $ */
2: /* $NetBSD: pcs_bus_io_common.c,v 1.14 1996/12/02 22:19:35 cgd Exp $ */
3:
4: /*
5: * Copyright (c) 1995, 1996 Carnegie-Mellon University.
6: * All rights reserved.
7: *
8: * Author: Chris G. Demetriou
9: *
10: * Permission to use, copy, modify and distribute this software and
11: * its documentation is hereby granted, provided that both the copyright
12: * notice and this permission notice appear in all copies of the
13: * software, derivative works or modified versions, and any portions
14: * thereof, and that both notices appear in supporting documentation.
15: *
16: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19: *
20: * Carnegie Mellon requests users of this software to return to
21: *
22: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23: * School of Computer Science
24: * Carnegie Mellon University
25: * Pittsburgh PA 15213-3890
26: *
27: * any improvements or extensions that they make and grant Carnegie the
28: * rights to redistribute these changes.
29: */
30:
31: /*
32: * Common PCI Chipset "bus I/O" functions, for chipsets which have to
33: * deal with only a single PCI interface chip in a machine.
34: *
35: * uses:
36: * CHIP name of the 'chip' it's being compiled for.
37: * CHIP_IO_BASE Sparse I/O space base to use.
38: */
39:
40: #include <sys/extent.h>
41:
42: #include <machine/bwx.h>
43:
44: #define __C(A,B) __CONCAT(A,B)
45: #define __S(S) __STRING(S)
46:
47: #ifndef CHIP_EXTENT_NAME
48: #define CHIP_EXTENT_NAME(v) __S(__C(CHIP,_bus_io))
49: #endif
50:
51: #ifndef CHIP_EXTENT_STORAGE
52: #define CHIP_EXTENT_STORAGE(v) __C(CHIP,_io_ex_storage)
53: static long
54: __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
55: #endif
56:
57: /* mapping/unmapping */
58: int __C(CHIP,_io_map)(void *, bus_addr_t, bus_size_t, int,
59: bus_space_handle_t *);
60: void __C(CHIP,_io_unmap)(void *, bus_space_handle_t,
61: bus_size_t);
62: int __C(CHIP,_io_subregion)(void *, bus_space_handle_t,
63: bus_size_t, bus_size_t, bus_space_handle_t *);
64:
65: /* allocation/deallocation */
66: int __C(CHIP,_io_alloc)(void *, bus_addr_t, bus_addr_t,
67: bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *,
68: bus_space_handle_t *);
69: void __C(CHIP,_io_free)(void *, bus_space_handle_t,
70: bus_size_t);
71:
72: /* barrier */
73: inline void __C(CHIP,_io_barrier)(void *, bus_space_handle_t,
74: bus_size_t, bus_size_t, int);
75:
76: /* read (single) */
77: inline u_int8_t __C(CHIP,_io_read_1)(void *, bus_space_handle_t,
78: bus_size_t);
79: inline u_int16_t __C(CHIP,_io_read_2)(void *, bus_space_handle_t,
80: bus_size_t);
81: inline u_int32_t __C(CHIP,_io_read_4)(void *, bus_space_handle_t,
82: bus_size_t);
83: inline u_int64_t __C(CHIP,_io_read_8)(void *, bus_space_handle_t,
84: bus_size_t);
85:
86: /* read multiple */
87: void __C(CHIP,_io_read_multi_1)(void *, bus_space_handle_t,
88: bus_size_t, u_int8_t *, bus_size_t);
89: void __C(CHIP,_io_read_multi_2)(void *, bus_space_handle_t,
90: bus_size_t, u_int16_t *, bus_size_t);
91: void __C(CHIP,_io_read_multi_4)(void *, bus_space_handle_t,
92: bus_size_t, u_int32_t *, bus_size_t);
93: void __C(CHIP,_io_read_multi_8)(void *, bus_space_handle_t,
94: bus_size_t, u_int64_t *, bus_size_t);
95:
96: /* read region */
97: void __C(CHIP,_io_read_region_1)(void *, bus_space_handle_t,
98: bus_size_t, u_int8_t *, bus_size_t);
99: void __C(CHIP,_io_read_region_2)(void *, bus_space_handle_t,
100: bus_size_t, u_int16_t *, bus_size_t);
101: void __C(CHIP,_io_read_region_4)(void *, bus_space_handle_t,
102: bus_size_t, u_int32_t *, bus_size_t);
103: void __C(CHIP,_io_read_region_8)(void *, bus_space_handle_t,
104: bus_size_t, u_int64_t *, bus_size_t);
105:
106: /* write (single) */
107: inline void __C(CHIP,_io_write_1)(void *, bus_space_handle_t,
108: bus_size_t, u_int8_t);
109: inline void __C(CHIP,_io_write_2)(void *, bus_space_handle_t,
110: bus_size_t, u_int16_t);
111: inline void __C(CHIP,_io_write_4)(void *, bus_space_handle_t,
112: bus_size_t, u_int32_t);
113: inline void __C(CHIP,_io_write_8)(void *, bus_space_handle_t,
114: bus_size_t, u_int64_t);
115:
116: /* write multiple */
117: void __C(CHIP,_io_write_multi_1)(void *, bus_space_handle_t,
118: bus_size_t, const u_int8_t *, bus_size_t);
119: void __C(CHIP,_io_write_multi_2)(void *, bus_space_handle_t,
120: bus_size_t, const u_int16_t *, bus_size_t);
121: void __C(CHIP,_io_write_multi_4)(void *, bus_space_handle_t,
122: bus_size_t, const u_int32_t *, bus_size_t);
123: void __C(CHIP,_io_write_multi_8)(void *, bus_space_handle_t,
124: bus_size_t, const u_int64_t *, bus_size_t);
125:
126: /* write region */
127: void __C(CHIP,_io_write_region_1)(void *, bus_space_handle_t,
128: bus_size_t, const u_int8_t *, bus_size_t);
129: void __C(CHIP,_io_write_region_2)(void *, bus_space_handle_t,
130: bus_size_t, const u_int16_t *, bus_size_t);
131: void __C(CHIP,_io_write_region_4)(void *, bus_space_handle_t,
132: bus_size_t, const u_int32_t *, bus_size_t);
133: void __C(CHIP,_io_write_region_8)(void *, bus_space_handle_t,
134: bus_size_t, const u_int64_t *, bus_size_t);
135:
136: /* set multiple */
137: void __C(CHIP,_io_set_multi_1)(void *, bus_space_handle_t,
138: bus_size_t, u_int8_t, bus_size_t);
139: void __C(CHIP,_io_set_multi_2)(void *, bus_space_handle_t,
140: bus_size_t, u_int16_t, bus_size_t);
141: void __C(CHIP,_io_set_multi_4)(void *, bus_space_handle_t,
142: bus_size_t, u_int32_t, bus_size_t);
143: void __C(CHIP,_io_set_multi_8)(void *, bus_space_handle_t,
144: bus_size_t, u_int64_t, bus_size_t);
145:
146: /* set region */
147: void __C(CHIP,_io_set_region_1)(void *, bus_space_handle_t,
148: bus_size_t, u_int8_t, bus_size_t);
149: void __C(CHIP,_io_set_region_2)(void *, bus_space_handle_t,
150: bus_size_t, u_int16_t, bus_size_t);
151: void __C(CHIP,_io_set_region_4)(void *, bus_space_handle_t,
152: bus_size_t, u_int32_t, bus_size_t);
153: void __C(CHIP,_io_set_region_8)(void *, bus_space_handle_t,
154: bus_size_t, u_int64_t, bus_size_t);
155:
156: /* copy */
157: void __C(CHIP,_io_copy_1)(void *, bus_space_handle_t,
158: bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
159: void __C(CHIP,_io_copy_2)(void *, bus_space_handle_t,
160: bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
161: void __C(CHIP,_io_copy_4)(void *, bus_space_handle_t,
162: bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
163: void __C(CHIP,_io_copy_8)(void *, bus_space_handle_t,
164: bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
165:
166: /* read multiple raw */
167: void __C(CHIP,_io_read_raw_multi_2)(void *, bus_space_handle_t,
168: bus_size_t, u_int8_t *, bus_size_t);
169: void __C(CHIP,_io_read_raw_multi_4)(void *, bus_space_handle_t,
170: bus_size_t, u_int8_t *, bus_size_t);
171: void __C(CHIP,_io_read_raw_multi_8)(void *, bus_space_handle_t,
172: bus_size_t, u_int8_t *, bus_size_t);
173:
174: /* write multiple raw */
175: void __C(CHIP,_io_write_raw_multi_2)(void *,
176: bus_space_handle_t, bus_size_t, const u_int8_t *,
177: bus_size_t);
178: void __C(CHIP,_io_write_raw_multi_4)(void *,
179: bus_space_handle_t, bus_size_t, const u_int8_t *,
180: bus_size_t);
181: void __C(CHIP,_io_write_raw_multi_8)(void *,
182: bus_space_handle_t, bus_size_t, const u_int8_t *,
183: bus_size_t);
184:
185: void
186: __C(CHIP,_bus_io_init)(t, v)
187: bus_space_tag_t t;
188: void *v;
189: {
190: struct extent *ex;
191:
192: /*
193: * Initialize the bus space tag.
194: */
195:
196: /* cookie */
197: t->abs_cookie = v;
198:
199: /* mapping/unmapping */
200: t->abs_map = __C(CHIP,_io_map);
201: t->abs_unmap = __C(CHIP,_io_unmap);
202: t->abs_subregion = __C(CHIP,_io_subregion);
203:
204: /* allocation/deallocation */
205: t->abs_alloc = __C(CHIP,_io_alloc);
206: t->abs_free = __C(CHIP,_io_free);
207:
208: /* barrier */
209: t->abs_barrier = __C(CHIP,_io_barrier);
210:
211: /* read (single) */
212: t->abs_r_1 = __C(CHIP,_io_read_1);
213: t->abs_r_2 = __C(CHIP,_io_read_2);
214: t->abs_r_4 = __C(CHIP,_io_read_4);
215: t->abs_r_8 = __C(CHIP,_io_read_8);
216:
217: /* read multiple */
218: t->abs_rm_1 = __C(CHIP,_io_read_multi_1);
219: t->abs_rm_2 = __C(CHIP,_io_read_multi_2);
220: t->abs_rm_4 = __C(CHIP,_io_read_multi_4);
221: t->abs_rm_8 = __C(CHIP,_io_read_multi_8);
222:
223: /* read region */
224: t->abs_rr_1 = __C(CHIP,_io_read_region_1);
225: t->abs_rr_2 = __C(CHIP,_io_read_region_2);
226: t->abs_rr_4 = __C(CHIP,_io_read_region_4);
227: t->abs_rr_8 = __C(CHIP,_io_read_region_8);
228:
229: /* write (single) */
230: t->abs_w_1 = __C(CHIP,_io_write_1);
231: t->abs_w_2 = __C(CHIP,_io_write_2);
232: t->abs_w_4 = __C(CHIP,_io_write_4);
233: t->abs_w_8 = __C(CHIP,_io_write_8);
234:
235: /* write multiple */
236: t->abs_wm_1 = __C(CHIP,_io_write_multi_1);
237: t->abs_wm_2 = __C(CHIP,_io_write_multi_2);
238: t->abs_wm_4 = __C(CHIP,_io_write_multi_4);
239: t->abs_wm_8 = __C(CHIP,_io_write_multi_8);
240:
241: /* write region */
242: t->abs_wr_1 = __C(CHIP,_io_write_region_1);
243: t->abs_wr_2 = __C(CHIP,_io_write_region_2);
244: t->abs_wr_4 = __C(CHIP,_io_write_region_4);
245: t->abs_wr_8 = __C(CHIP,_io_write_region_8);
246:
247: /* set multiple */
248: t->abs_sm_1 = __C(CHIP,_io_set_multi_1);
249: t->abs_sm_2 = __C(CHIP,_io_set_multi_2);
250: t->abs_sm_4 = __C(CHIP,_io_set_multi_4);
251: t->abs_sm_8 = __C(CHIP,_io_set_multi_8);
252:
253: /* set region */
254: t->abs_sr_1 = __C(CHIP,_io_set_region_1);
255: t->abs_sr_2 = __C(CHIP,_io_set_region_2);
256: t->abs_sr_4 = __C(CHIP,_io_set_region_4);
257: t->abs_sr_8 = __C(CHIP,_io_set_region_8);
258:
259: /* copy */
260: t->abs_c_1 = __C(CHIP,_io_copy_1);
261: t->abs_c_2 = __C(CHIP,_io_copy_2);
262: t->abs_c_4 = __C(CHIP,_io_copy_4);
263: t->abs_c_8 = __C(CHIP,_io_copy_8);
264:
265: /* read multiple raw */
266: t->abs_rrm_2 = __C(CHIP,_io_read_raw_multi_2);
267: t->abs_rrm_4 = __C(CHIP,_io_read_raw_multi_4);
268: t->abs_rrm_8 = __C(CHIP,_io_read_raw_multi_8);
269:
270: /* write multiple raw*/
271: t->abs_wrm_2 = __C(CHIP,_io_write_raw_multi_2);
272: t->abs_wrm_4 = __C(CHIP,_io_write_raw_multi_4);
273: t->abs_wrm_8 = __C(CHIP,_io_write_raw_multi_8);
274:
275: ex = extent_create(CHIP_EXTENT_NAME(v), 0x0UL, 0xffffffffUL,
276: M_DEVBUF, (caddr_t)CHIP_EXTENT_STORAGE(v),
277: sizeof(CHIP_EXTENT_STORAGE(v)), EX_NOWAIT|EX_NOCOALESCE);
278:
279: CHIP_IO_EXTENT(v) = ex;
280: }
281:
282: int
283: __C(CHIP,_io_map)(v, ioaddr, iosize, cacheable, iohp)
284: void *v;
285: bus_addr_t ioaddr;
286: bus_size_t iosize;
287: int cacheable;
288: bus_space_handle_t *iohp;
289: {
290: int error;
291:
292: #ifdef EXTENT_DEBUG
293: printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1);
294: #endif
295: error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize,
296: EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0));
297: if (error) {
298: #ifdef EXTENT_DEBUG
299: printf("io: allocation failed (%d)\n", error);
300: extent_print(CHIP_IO_EXTENT(v));
301: #endif
302: return (error);
303: }
304:
305: *iohp = ALPHA_PHYS_TO_K0SEG(CHIP_IO_SYS_START(v)) + ioaddr;
306:
307: return (0);
308: }
309:
310: void
311: __C(CHIP,_io_unmap)(v, ioh, iosize)
312: void *v;
313: bus_space_handle_t ioh;
314: bus_size_t iosize;
315: {
316: bus_addr_t ioaddr;
317: int error;
318:
319: #ifdef EXTENT_DEBUG
320: printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize);
321: #endif
322:
323: ioaddr = ioh - ALPHA_PHYS_TO_K0SEG(CHIP_IO_SYS_START(v));
324:
325: #ifdef EXTENT_DEBUG
326: printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1);
327: #endif
328: error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize,
329: EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0));
330: if (error) {
331: printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n",
332: __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1,
333: error);
334: #ifdef EXTENT_DEBUG
335: extent_print(CHIP_IO_EXTENT(v));
336: #endif
337: }
338: }
339:
340: int
341: __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh)
342: void *v;
343: bus_space_handle_t ioh, *nioh;
344: bus_size_t offset, size;
345: {
346:
347: *nioh = ioh + offset;
348: return (0);
349: }
350:
351: int
352: __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, cacheable,
353: addrp, bshp)
354: void *v;
355: bus_addr_t rstart, rend, *addrp;
356: bus_size_t size, align, boundary;
357: int cacheable;
358: bus_space_handle_t *bshp;
359: {
360:
361: /* XXX XXX XXX XXX XXX XXX */
362: panic("%s not implemented", __S(__C(CHIP,_io_alloc)));
363: }
364:
365: void
366: __C(CHIP,_io_free)(v, bsh, size)
367: void *v;
368: bus_space_handle_t bsh;
369: bus_size_t size;
370: {
371:
372: /* XXX XXX XXX XXX XXX XXX */
373: panic("%s not implemented", __S(__C(CHIP,_io_free)));
374: }
375:
376: inline void
377: __C(CHIP,_io_barrier)(v, h, o, l, f)
378: void *v;
379: bus_space_handle_t h;
380: bus_size_t o, l;
381: int f;
382: {
383:
384: if ((f & BUS_BARRIER_READ) != 0)
385: alpha_mb();
386: else if ((f & BUS_BARRIER_WRITE) != 0)
387: alpha_wmb();
388: }
389:
390: inline u_int8_t
391: __C(CHIP,_io_read_1)(v, ioh, off)
392: void *v;
393: bus_space_handle_t ioh;
394: bus_size_t off;
395: {
396: bus_addr_t addr;
397:
398: addr = ioh + off;
399: alpha_mb();
400: return (alpha_ldbu((u_int8_t *)addr));
401: }
402:
403: inline u_int16_t
404: __C(CHIP,_io_read_2)(v, ioh, off)
405: void *v;
406: bus_space_handle_t ioh;
407: bus_size_t off;
408: {
409: bus_addr_t addr;
410:
411: addr = ioh + off;
412: #ifdef DIAGNOSTIC
413: if (addr & 1)
414: panic(__S(__C(CHIP,_io_read_2)) ": addr 0x%lx not aligned",
415: addr);
416: #endif
417: alpha_mb();
418: return (alpha_ldwu((u_int16_t *)addr));
419: }
420:
421: inline u_int32_t
422: __C(CHIP,_io_read_4)(v, ioh, off)
423: void *v;
424: bus_space_handle_t ioh;
425: bus_size_t off;
426: {
427: bus_addr_t addr;
428:
429: addr = ioh + off;
430: #ifdef DIAGNOSTIC
431: if (addr & 3)
432: panic(__S(__C(CHIP,_io_read_4)) ": addr 0x%lx not aligned",
433: addr);
434: #endif
435: alpha_mb();
436: return (*(u_int32_t *)addr);
437: }
438:
439: inline u_int64_t
440: __C(CHIP,_io_read_8)(v, ioh, off)
441: void *v;
442: bus_space_handle_t ioh;
443: bus_size_t off;
444: {
445:
446: /* XXX XXX XXX */
447: panic("%s not implemented", __S(__C(CHIP,_io_read_8)));
448: }
449:
450: #define CHIP_io_read_multi_N(BYTES,TYPE) \
451: void \
452: __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \
453: void *v; \
454: bus_space_handle_t h; \
455: bus_size_t o, c; \
456: TYPE *a; \
457: { \
458: \
459: while (c-- > 0) { \
460: __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \
461: BUS_BARRIER_READ); \
462: *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \
463: } \
464: }
465: CHIP_io_read_multi_N(1,u_int8_t)
466: CHIP_io_read_multi_N(2,u_int16_t)
467: CHIP_io_read_multi_N(4,u_int32_t)
468: CHIP_io_read_multi_N(8,u_int64_t)
469:
470: #define CHIP_io_read_region_N(BYTES,TYPE) \
471: void \
472: __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \
473: void *v; \
474: bus_space_handle_t h; \
475: bus_size_t o, c; \
476: TYPE *a; \
477: { \
478: \
479: while (c-- > 0) { \
480: *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \
481: o += sizeof *a; \
482: } \
483: }
484: CHIP_io_read_region_N(1,u_int8_t)
485: CHIP_io_read_region_N(2,u_int16_t)
486: CHIP_io_read_region_N(4,u_int32_t)
487: CHIP_io_read_region_N(8,u_int64_t)
488:
489: inline void
490: __C(CHIP,_io_write_1)(v, ioh, off, val)
491: void *v;
492: bus_space_handle_t ioh;
493: bus_size_t off;
494: u_int8_t val;
495: {
496: bus_addr_t addr;
497:
498: addr = ioh + off;
499: alpha_stb((u_int8_t *)addr, val);
500: alpha_mb();
501: }
502:
503: inline void
504: __C(CHIP,_io_write_2)(v, ioh, off, val)
505: void *v;
506: bus_space_handle_t ioh;
507: bus_size_t off;
508: u_int16_t val;
509: {
510: bus_addr_t addr;
511:
512: addr = ioh + off;
513: #ifdef DIAGNOSTIC
514: if (addr & 1)
515: panic(__S(__C(CHIP,_io_write_2)) ": addr 0x%lx not aligned",
516: addr);
517: #endif
518: alpha_stw((u_int16_t *)addr, val);
519: alpha_mb();
520: }
521:
522: inline void
523: __C(CHIP,_io_write_4)(v, ioh, off, val)
524: void *v;
525: bus_space_handle_t ioh;
526: bus_size_t off;
527: u_int32_t val;
528: {
529: bus_addr_t addr;
530:
531: addr = ioh + off;
532: #ifdef DIAGNOSTIC
533: if (addr & 3)
534: panic(__S(__C(CHIP,_io_write_4)) ": addr 0x%lx not aligned",
535: addr);
536: #endif
537: *(u_int32_t *)addr = val;
538: alpha_mb();
539: }
540:
541: inline void
542: __C(CHIP,_io_write_8)(v, ioh, off, val)
543: void *v;
544: bus_space_handle_t ioh;
545: bus_size_t off;
546: u_int64_t val;
547: {
548:
549: /* XXX XXX XXX */
550: panic("%s not implemented", __S(__C(CHIP,_io_write_8)));
551: alpha_mb();
552: }
553:
554: #define CHIP_io_write_multi_N(BYTES,TYPE) \
555: void \
556: __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \
557: void *v; \
558: bus_space_handle_t h; \
559: bus_size_t o, c; \
560: const TYPE *a; \
561: { \
562: \
563: while (c-- > 0) { \
564: __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \
565: __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \
566: BUS_BARRIER_WRITE); \
567: } \
568: }
569: CHIP_io_write_multi_N(1,u_int8_t)
570: CHIP_io_write_multi_N(2,u_int16_t)
571: CHIP_io_write_multi_N(4,u_int32_t)
572: CHIP_io_write_multi_N(8,u_int64_t)
573:
574: #define CHIP_io_write_region_N(BYTES,TYPE) \
575: void \
576: __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \
577: void *v; \
578: bus_space_handle_t h; \
579: bus_size_t o, c; \
580: const TYPE *a; \
581: { \
582: \
583: while (c-- > 0) { \
584: __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \
585: o += sizeof *a; \
586: } \
587: }
588: CHIP_io_write_region_N(1,u_int8_t)
589: CHIP_io_write_region_N(2,u_int16_t)
590: CHIP_io_write_region_N(4,u_int32_t)
591: CHIP_io_write_region_N(8,u_int64_t)
592:
593: #define CHIP_io_set_multi_N(BYTES,TYPE) \
594: void \
595: __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \
596: void *v; \
597: bus_space_handle_t h; \
598: bus_size_t o, c; \
599: TYPE val; \
600: { \
601: \
602: while (c-- > 0) { \
603: __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \
604: __C(CHIP,_io_barrier)(v, h, o, sizeof val, \
605: BUS_BARRIER_WRITE); \
606: } \
607: }
608: CHIP_io_set_multi_N(1,u_int8_t)
609: CHIP_io_set_multi_N(2,u_int16_t)
610: CHIP_io_set_multi_N(4,u_int32_t)
611: CHIP_io_set_multi_N(8,u_int64_t)
612:
613: #define CHIP_io_set_region_N(BYTES,TYPE) \
614: void \
615: __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \
616: void *v; \
617: bus_space_handle_t h; \
618: bus_size_t o, c; \
619: TYPE val; \
620: { \
621: \
622: while (c-- > 0) { \
623: __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \
624: o += sizeof val; \
625: } \
626: }
627: CHIP_io_set_region_N(1,u_int8_t)
628: CHIP_io_set_region_N(2,u_int16_t)
629: CHIP_io_set_region_N(4,u_int32_t)
630: CHIP_io_set_region_N(8,u_int64_t)
631:
632: #define CHIP_io_copy_N(BYTES) \
633: void \
634: __C(__C(CHIP,_io_copy_),BYTES)(v, h1, o1, h2, o2, c) \
635: void *v; \
636: bus_space_handle_t h1, h2; \
637: bus_size_t o1, o2, c; \
638: { \
639: bus_size_t i, o; \
640: \
641: for (i = 0, o = 0; i < c; i++, o += BYTES) \
642: __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \
643: __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \
644: }
645: CHIP_io_copy_N(1)
646: CHIP_io_copy_N(2)
647: CHIP_io_copy_N(4)
648: CHIP_io_copy_N(8)
649:
650: #define CHIP_io_read_raw_multi_N(BYTES,TYPE) \
651: void \
652: __C(__C(CHIP,_io_read_raw_multi_),BYTES)(v, h, o, a, c) \
653: void *v; \
654: bus_space_handle_t h; \
655: bus_size_t o, c; \
656: u_int8_t *a; \
657: { \
658: TYPE temp; \
659: int i; \
660: \
661: while (c > 0) { \
662: __C(CHIP,_io_barrier)(v, h, o, BYTES, BUS_BARRIER_READ); \
663: temp = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \
664: i = MIN(c, BYTES); \
665: c -= i; \
666: while (i--) { \
667: *a++ = temp & 0xff; \
668: temp >>= 8; \
669: } \
670: } \
671: }
672: CHIP_io_read_raw_multi_N(2,u_int16_t)
673: CHIP_io_read_raw_multi_N(4,u_int32_t)
674: CHIP_io_read_raw_multi_N(8,u_int64_t)
675:
676: #define CHIP_io_write_raw_multi_N(BYTES,TYPE) \
677: void \
678: __C(__C(CHIP,_io_write_raw_multi_),BYTES)(v, h, o, a, c) \
679: void *v; \
680: bus_space_handle_t h; \
681: bus_size_t o, c; \
682: const u_int8_t *a; \
683: { \
684: TYPE temp; \
685: int i; \
686: \
687: while (c > 0) { \
688: temp = 0; \
689: for (i = BYTES - 1; i >= 0; i--) { \
690: temp <<= 8; \
691: if (i < c) \
692: temp |= *(a + i); \
693: } \
694: __C(__C(CHIP,_io_write_),BYTES)(v, h, o, temp); \
695: __C(CHIP,_io_barrier)(v, h, o, BYTES, BUS_BARRIER_WRITE); \
696: i = MIN(c, BYTES); \
697: c -= i; \
698: a += i; \
699: } \
700: }
701: CHIP_io_write_raw_multi_N(2,u_int16_t)
702: CHIP_io_write_raw_multi_N(4,u_int32_t)
703: CHIP_io_write_raw_multi_N(8,u_int64_t)