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1.1 nbrk 1: /* $OpenBSD: pci_2100_a50.c,v 1.20 2006/06/15 20:08:29 brad Exp $ */
2: /* $NetBSD: pci_2100_a50.c,v 1.12 1996/11/13 21:13:29 cgd Exp $ */
3:
4: /*
5: * Copyright (c) 1995, 1996 Carnegie-Mellon University.
6: * All rights reserved.
7: *
8: * Author: Chris G. Demetriou
9: *
10: * Permission to use, copy, modify and distribute this software and
11: * its documentation is hereby granted, provided that both the copyright
12: * notice and this permission notice appear in all copies of the
13: * software, derivative works or modified versions, and any portions
14: * thereof, and that both notices appear in supporting documentation.
15: *
16: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19: *
20: * Carnegie Mellon requests users of this software to return to
21: *
22: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23: * School of Computer Science
24: * Carnegie Mellon University
25: * Pittsburgh PA 15213-3890
26: *
27: * any improvements or extensions that they make and grant Carnegie the
28: * rights to redistribute these changes.
29: */
30:
31: #include <sys/types.h>
32: #include <sys/param.h>
33: #include <sys/time.h>
34: #include <sys/systm.h>
35: #include <sys/errno.h>
36: #include <sys/device.h>
37: #include <uvm/uvm_extern.h>
38:
39: #include <machine/autoconf.h>
40: #include <machine/bus.h>
41: #include <machine/intr.h>
42:
43: #include <dev/isa/isavar.h>
44: #include <dev/pci/pcireg.h>
45: #include <dev/pci/pcivar.h>
46:
47: #include <alpha/pci/apecsvar.h>
48:
49: #include <alpha/pci/pci_2100_a50.h>
50: #include <alpha/pci/siovar.h>
51: #include <alpha/pci/sioreg.h>
52:
53: #include "sio.h"
54:
55: int dec_2100_a50_intr_map(void *, pcitag_t, int, int,
56: pci_intr_handle_t *);
57: const char *dec_2100_a50_intr_string(void *, pci_intr_handle_t);
58: int dec_2100_a50_intr_line(void *, pci_intr_handle_t);
59: void *dec_2100_a50_intr_establish(void *, pci_intr_handle_t,
60: int, int (*func)(void *), void *, char *);
61: void dec_2100_a50_intr_disestablish(void *, void *);
62:
63: #define APECS_SIO_DEVICE 7 /* XXX */
64:
65: void
66: pci_2100_a50_pickintr(acp)
67: struct apecs_config *acp;
68: {
69: bus_space_tag_t iot = &acp->ac_iot;
70: pci_chipset_tag_t pc = &acp->ac_pc;
71: pcireg_t sioclass;
72: int sioII;
73:
74: /* XXX MAGIC NUMBER */
75: sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), PCI_CLASS_REG);
76: sioII = (sioclass & 0xff) >= 3;
77:
78: if (!sioII)
79: printf("WARNING: SIO NOT SIO II... NO BETS...\n");
80:
81: pc->pc_intr_v = acp;
82: pc->pc_intr_map = dec_2100_a50_intr_map;
83: pc->pc_intr_string = dec_2100_a50_intr_string;
84: pc->pc_intr_line = dec_2100_a50_intr_line;
85: pc->pc_intr_establish = dec_2100_a50_intr_establish;
86: pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish;
87:
88: /* Not supported on 2100 A50. */
89: pc->pc_pciide_compat_intr_establish = NULL;
90: pc->pc_pciide_compat_intr_disestablish = NULL;
91:
92: #if NSIO
93: sio_intr_setup(pc, iot);
94: #else
95: panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)");
96: #endif
97: }
98:
99: int
100: dec_2100_a50_intr_map(acv, bustag, buspin, line, ihp)
101: void *acv;
102: pcitag_t bustag;
103: int buspin, line;
104: pci_intr_handle_t *ihp;
105: {
106: struct apecs_config *acp = acv;
107: pci_chipset_tag_t pc = &acp->ac_pc;
108: int device, pirq;
109: pcireg_t pirqreg;
110: u_int8_t pirqline;
111:
112: if (buspin == 0) {
113: /* No IRQ used. */
114: return 1;
115: }
116: if (buspin > 4) {
117: printf("dec_2100_a50_intr_map: bad interrupt pin %d\n",
118: buspin);
119: return 1;
120: }
121:
122: pci_decompose_tag(pc, bustag, NULL, &device, NULL);
123:
124: switch (device) {
125: case 6: /* NCR SCSI */
126: pirq = 3;
127: break;
128:
129: case 11: /* slot 1 */
130: case 14: /* slot 3 */
131: switch (buspin) {
132: case PCI_INTERRUPT_PIN_A:
133: case PCI_INTERRUPT_PIN_D:
134: pirq = 0;
135: break;
136: case PCI_INTERRUPT_PIN_B:
137: pirq = 2;
138: break;
139: case PCI_INTERRUPT_PIN_C:
140: pirq = 1;
141: break;
142: #ifdef DIAGNOSTIC
143: default: /* XXX gcc -Wuninitialized */
144: panic("dec_2100_a50_intr_map bogus PCI pin %d",
145: buspin);
146: #endif
147: };
148: break;
149:
150: case 12: /* slot 2 */
151: switch (buspin) {
152: case PCI_INTERRUPT_PIN_A:
153: case PCI_INTERRUPT_PIN_D:
154: pirq = 1;
155: break;
156: case PCI_INTERRUPT_PIN_B:
157: pirq = 0;
158: break;
159: case PCI_INTERRUPT_PIN_C:
160: pirq = 2;
161: break;
162: #ifdef DIAGNOSTIC
163: default: /* XXX gcc -Wuninitialized */
164: panic("dec_2100_a50_intr_map bogus PCI pin %d",
165: buspin);
166: #endif
167: };
168: break;
169:
170: case 13: /* slot 3 */
171: switch (buspin) {
172: case PCI_INTERRUPT_PIN_A:
173: case PCI_INTERRUPT_PIN_D:
174: pirq = 2;
175: break;
176: case PCI_INTERRUPT_PIN_B:
177: pirq = 1;
178: break;
179: case PCI_INTERRUPT_PIN_C:
180: pirq = 0;
181: break;
182: #ifdef DIAGNOSTIC
183: default: /* XXX gcc -Wuninitialized */
184: panic("dec_2100_a50_intr_map bogus PCI pin %d",
185: buspin);
186: #endif
187: };
188: break;
189:
190: default:
191: printf("dec_2100_a50_intr_map: weird device number %d\n",
192: device);
193: return 1;
194: }
195:
196: pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, APECS_SIO_DEVICE, 0),
197: SIO_PCIREG_PIRQ_RTCTRL);
198: #if 0
199: printf("pci_2100_a50_map_int: device %d pin %c: pirq %d, reg = %x\n",
200: device, '@' + buspin, pirq, pirqreg);
201: #endif
202: pirqline = (pirqreg >> (pirq * 8)) & 0xff;
203: if ((pirqline & 0x80) != 0)
204: return 1;
205: pirqline &= 0xf;
206:
207: #if 0
208: printf("pci_2100_a50_map_int: device %d pin %c: mapped to line %d\n",
209: device, '@' + buspin, pirqline);
210: #endif
211:
212: *ihp = pirqline;
213: return (0);
214: }
215:
216: const char *
217: dec_2100_a50_intr_string(acv, ih)
218: void *acv;
219: pci_intr_handle_t ih;
220: {
221: return sio_intr_string(NULL /*XXX*/, ih);
222: }
223:
224: int
225: dec_2100_a50_intr_line(acv, ih)
226: void *acv;
227: pci_intr_handle_t ih;
228: {
229: return sio_intr_line(NULL /*XXX*/, ih);
230: }
231:
232: void *
233: dec_2100_a50_intr_establish(acv, ih, level, func, arg, name)
234: void *acv, *arg;
235: pci_intr_handle_t ih;
236: int level;
237: int (*func)(void *);
238: char *name;
239: {
240: return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func,
241: arg, name);
242: }
243:
244: void
245: dec_2100_a50_intr_disestablish(acv, cookie)
246: void *acv, *cookie;
247: {
248: sio_intr_disestablish(NULL /*XXX*/, cookie);
249: }