Annotation of sys/arch/alpha/pci/pci_1000a.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: pci_1000a.c,v 1.5 2006/06/15 20:08:29 brad Exp $ */
2: /* $NetBSD: pci_1000a.c,v 1.14 2001/07/27 00:25:20 thorpej Exp $ */
3:
4: /*
5: * Copyright (c) 1998 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is based on pci_kn20aa.c, written by Chris G. Demetriou at
9: * Carnegie-Mellon University. Platform support for Noritake, Pintake, and
10: * Corelle by Ross Harvey with copyright assignment by permission of Avalon
11: * Computer Systems, Inc.
12: *
13: * Redistribution and use in source and binary forms, with or without
14: * modification, are permitted provided that the following conditions
15: * are met:
16: * 1. Redistributions of source code must retain the above copyright
17: * notice, this list of conditions and the following disclaimer.
18: * 2. Redistributions in binary form must reproduce the above copyright
19: * notice, this list of conditions and the following disclaimer in the
20: * documentation and/or other materials provided with the distribution.
21: * 3. All advertising materials mentioning features or use of this software
22: * must display the following acknowledgement:
23: * This product includes software developed by the NetBSD
24: * Foundation, Inc. and its contributors.
25: * 4. Neither the name of The NetBSD Foundation nor the names of its
26: * contributors may be used to endorse or promote products derived
27: * from this software without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
30: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
32: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
33: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39: * POSSIBILITY OF SUCH DAMAGE.
40: */
41:
42: /*
43: * Copyright (c) 1995, 1996 Carnegie-Mellon University.
44: * All rights reserved.
45: *
46: * Author: Chris G. Demetriou
47: *
48: * Permission to use, copy, modify and distribute this software and
49: * its documentation is hereby granted, provided that both the copyright
50: * notice and this permission notice appear in all copies of the
51: * software, derivative works or modified versions, and any portions
52: * thereof, and that both notices appear in supporting documentation.
53: *
54: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
55: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
56: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
57: *
58: * Carnegie Mellon requests users of this software to return to
59: *
60: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
61: * School of Computer Science
62: * Carnegie Mellon University
63: * Pittsburgh PA 15213-3890
64: *
65: * any improvements or extensions that they make and grant Carnegie the
66: * rights to redistribute these changes.
67: */
68:
69: #include <sys/types.h>
70: #include <sys/param.h>
71: #include <sys/time.h>
72: #include <sys/systm.h>
73: #include <sys/errno.h>
74: #include <sys/malloc.h>
75: #include <sys/device.h>
76:
77: #include <uvm/uvm_extern.h>
78:
79: #include <machine/autoconf.h>
80:
81: #include <dev/pci/pcireg.h>
82: #include <dev/pci/pcivar.h>
83:
84: #include <alpha/pci/pci_1000a.h>
85:
86: #include "sio.h"
87: #if NSIO > 0 || NPCEB > 0
88: #include <alpha/pci/siovar.h>
89: #endif
90:
91: #define PCI_NIRQ 32
92: #define PCI_STRAY_MAX 5
93:
94: #define IMR2IRQ(bn) ((bn) - 1)
95: #define IRQ2IMR(irq) ((irq) + 1)
96:
97: static bus_space_tag_t mystery_icu_iot;
98: static bus_space_handle_t mystery_icu_ioh[2];
99:
100: int dec_1000a_intr_map(void *, pcitag_t, int, int,
101: pci_intr_handle_t *);
102: const char *dec_1000a_intr_string(void *, pci_intr_handle_t);
103: int dec_1000a_intr_line(void *, pci_intr_handle_t);
104: void *dec_1000a_intr_establish(void *, pci_intr_handle_t,
105: int, int (*func)(void *), void *, char *);
106: void dec_1000a_intr_disestablish(void *, void *);
107:
108: struct alpha_shared_intr *dec_1000a_pci_intr;
109:
110: void dec_1000a_iointr(void *arg, unsigned long vec);
111: void dec_1000a_enable_intr(int irq);
112: void dec_1000a_disable_intr(int irq);
113: void pci_1000a_imi(void);
114: static pci_chipset_tag_t pc_tag;
115:
116: void
117: pci_1000a_pickintr(core, iot, memt, pc)
118: void *core;
119: bus_space_tag_t iot, memt;
120: pci_chipset_tag_t pc;
121: {
122: #if 0
123: char *cp;
124: #endif
125: int i;
126:
127: mystery_icu_iot = iot;
128:
129: pc_tag = pc;
130: if (bus_space_map(iot, 0x54a, 2, 0, mystery_icu_ioh + 0)
131: || bus_space_map(iot, 0x54c, 2, 0, mystery_icu_ioh + 1))
132: panic("pci_1000a_pickintr");
133: pc->pc_intr_v = core;
134: pc->pc_intr_map = dec_1000a_intr_map;
135: pc->pc_intr_string = dec_1000a_intr_string;
136: pc->pc_intr_line = dec_1000a_intr_line;
137: pc->pc_intr_establish = dec_1000a_intr_establish;
138: pc->pc_intr_disestablish = dec_1000a_intr_disestablish;
139:
140: pc->pc_pciide_compat_intr_establish = NULL;
141: pc->pc_pciide_compat_intr_disestablish = NULL;
142:
143: dec_1000a_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ);
144: for (i = 0; i < PCI_NIRQ; i++) {
145: alpha_shared_intr_set_maxstrays(dec_1000a_pci_intr, i,
146: PCI_STRAY_MAX);
147: }
148:
149: pci_1000a_imi();
150: #if NSIO > 0 || NPCEB > 0
151: sio_intr_setup(pc, iot);
152: #endif
153: }
154:
155: int
156: dec_1000a_intr_map(ccv, bustag, buspin, line, ihp)
157: void *ccv;
158: pcitag_t bustag;
159: int buspin, line;
160: pci_intr_handle_t *ihp;
161: {
162: int imrbit, device;
163: /*
164: * Get bit number in mystery ICU imr
165: */
166: static const signed char imrmap[][4] = {
167: # define IRQSPLIT(o) { (o), (o)+1, (o)+16, (o)+16+1 }
168: # define IRQNONE { 0, 0, 0, 0 }
169: /* 0 */ { 1, 0, 0, 0 }, /* Noritake and Pintake */
170: /* 1 */ IRQSPLIT(8),
171: /* 2 */ IRQSPLIT(10),
172: /* 3 */ IRQSPLIT(12),
173: /* 4 */ IRQSPLIT(14),
174: /* 5 */ { 1, 0, 0, 0 }, /* Corelle */
175: /* 6 */ { 10, 0, 0, 0 }, /* Corelle */
176: /* 7 */ IRQNONE,
177: /* 8 */ { 1, 0, 0, 0 }, /* isp behind ppb */
178: /* 9 */ IRQNONE,
179: /* 10 */ IRQNONE,
180: /* 11 */ IRQSPLIT(2),
181: /* 12 */ IRQSPLIT(4),
182: /* 13 */ IRQSPLIT(6),
183: /* 14 */ IRQSPLIT(8) /* Corelle */
184: };
185:
186: if (buspin == 0) /* No IRQ used. */
187: return 1;
188: if (!(1 <= buspin && buspin <= 4))
189: goto bad;
190: pci_decompose_tag(pc_tag, bustag, NULL, &device, NULL);
191: if (0 <= device && device < sizeof imrmap / sizeof imrmap[0]) {
192: if (device == 0)
193: printf("dec_1000a_intr_map: ?! UNEXPECTED DEV 0\n");
194: imrbit = imrmap[device][buspin - 1];
195: if (imrbit) {
196: *ihp = IMR2IRQ(imrbit);
197: return 0;
198: }
199: }
200: bad: printf("dec_1000a_intr_map: can't map dev %d pin %d\n", device, buspin);
201: return 1;
202: }
203:
204: const char *
205: dec_1000a_intr_string(ccv, ih)
206: void *ccv;
207: pci_intr_handle_t ih;
208: {
209: static const char irqmsg_fmt[] = "dec_1000a irq %ld";
210: static char irqstr[sizeof irqmsg_fmt];
211:
212:
213: if (ih >= PCI_NIRQ)
214: panic("dec_1000a_intr_string: bogus dec_1000a IRQ 0x%lx", ih);
215:
216: snprintf(irqstr, sizeof irqstr, irqmsg_fmt, ih);
217: return (irqstr);
218: }
219:
220: int
221: dec_1000a_intr_line(ccv, ih)
222: void *ccv;
223: pci_intr_handle_t ih;
224: {
225: #if NSIO > 0
226: return sio_intr_line(NULL /*XXX*/, ih);
227: #else
228: return (ih);
229: #endif
230: }
231:
232: void *
233: dec_1000a_intr_establish(ccv, ih, level, func, arg, name)
234: void *ccv;
235: pci_intr_handle_t ih;
236: int level;
237: int (*func)(void *);
238: void *arg;
239: char *name;
240: {
241: void *cookie;
242:
243: if (ih >= PCI_NIRQ)
244: panic("dec_1000a_intr_establish: IRQ too high, 0x%lx", ih);
245:
246: cookie = alpha_shared_intr_establish(dec_1000a_pci_intr, ih, IST_LEVEL,
247: level, func, arg, name);
248:
249: if (cookie != NULL &&
250: alpha_shared_intr_firstactive(dec_1000a_pci_intr, ih)) {
251: scb_set(0x900 + SCB_IDXTOVEC(ih), dec_1000a_iointr, NULL);
252: dec_1000a_enable_intr(ih);
253:
254: }
255: return (cookie);
256: }
257:
258: void
259: dec_1000a_intr_disestablish(ccv, cookie)
260: void *ccv, *cookie;
261: {
262: struct alpha_shared_intrhand *ih = cookie;
263: unsigned int irq = ih->ih_num;
264: int s;
265:
266: s = splhigh();
267:
268: alpha_shared_intr_disestablish(dec_1000a_pci_intr, cookie,
269: "dec_1000a irq");
270: if (alpha_shared_intr_isactive(dec_1000a_pci_intr, irq) == 0) {
271: dec_1000a_disable_intr(irq);
272: alpha_shared_intr_set_dfltsharetype(dec_1000a_pci_intr, irq,
273: IST_NONE);
274: scb_free(0x900 + SCB_IDXTOVEC(irq));
275: }
276:
277: splx(s);
278: }
279:
280: void
281: dec_1000a_iointr(framep, vec)
282: void *framep;
283: unsigned long vec;
284: {
285: int irq;
286:
287: irq = SCB_VECTOIDX(vec - 0x900);
288:
289: if (!alpha_shared_intr_dispatch(dec_1000a_pci_intr, irq)) {
290: alpha_shared_intr_stray(dec_1000a_pci_intr, irq,
291: "dec_1000a irq");
292: if (ALPHA_SHARED_INTR_DISABLE(dec_1000a_pci_intr, irq))
293: dec_1000a_disable_intr(irq);
294: } else
295: alpha_shared_intr_reset_strays(dec_1000a_pci_intr, irq);
296: }
297:
298: /*
299: * Read and write the mystery ICU IMR registers
300: */
301:
302: #define IR(h) bus_space_read_2(mystery_icu_iot, mystery_icu_ioh[h], 0)
303: #define IW(h, v) bus_space_write_2(mystery_icu_iot, mystery_icu_ioh[h], 0, (v))
304:
305: /*
306: * Enable and disable interrupts at the ICU level
307: */
308:
309: void
310: dec_1000a_enable_intr(irq)
311: int irq;
312: {
313: int imrval = IRQ2IMR(irq);
314: int i = imrval >= 16;
315:
316: IW(i, IR(i) | 1 << (imrval & 0xf));
317: }
318:
319: void
320: dec_1000a_disable_intr(irq)
321: int irq;
322: {
323: int imrval = IRQ2IMR(irq);
324: int i = imrval >= 16;
325:
326: IW(i, IR(i) & ~(1 << (imrval & 0xf)));
327: }
328: /*
329: * Initialize mystery ICU
330: */
331: void
332: pci_1000a_imi()
333: {
334: IW(0, IR(0) & 1);
335: IW(1, IR(0) & 3);
336: }
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